1. A Living Roadmap for Semiconductors A Living Roadmap for Semiconductors October 4, 2000 SRC Review Andrew B. Kahng UCSD CSE and ECE Departments* abk@ucsd.edu * effective January 1, 2001

2. 2 SRC Review 001004 abk Outline u The Design Technology Gap and the GSRC C.A.D. Theme u On Roadmaps u The GSRC Technology Extrapolation (GTX) System: Toward a Living Roadmap u A Living Roadmap for Semiconductors (and Design)

3. 3 SRC Review 001004 abk Motivation: The Design Technology Gap u Design Productivity Gap s Well-documented, threatens quality and value of designs  huge cost to semiconductor industry   huge cost to semiconductor industry u Most research: change the Design Problem, invent new algorithms... u Premise of MARCO GSRC “Calibrating Achievable Design” Theme: Design Productivity Gap == Design Technology Productivity Gap u Problem: Must improve Time-To-Market and Quality-of-Result for Design Technology u Goal: improve CAD Industry Productivity by changing how we specify, develop, and measure and improve Design Technology

4. 4 SRC Review 001004 abk Facets of the Design Technology Gap u Facets s No clear industry-wide R&D agenda s Time-to-Market: 5-7 years to get a leading-edge algorithm into production EDA  designers battle today’s design problems with yesterday’s design technology   designers battle today’s design problems with yesterday’s design technology s QOR: difficult to evaluate impact of new tools on overall design process s QOR: published descriptions insufficient for replication or even comparison of algorithms  CAD R&D cannot identify, evaluate or reuse the CAD technology leading edge research and innovation stall   CAD R&D cannot identify, evaluate or reuse the CAD technology leading edge  research and innovation stall u Causes s Lack of clear roadmapping for Design Technology w.r.t. ITRS, application markets s Lack of “Foundation CAD-IP”: interoperable, reusable, commodity infrastructure s Lack of resources, and relative over-resourcing of non-strategic, de facto commodity technology s Lack of standard metrics, benchmarks for Design Technology s More maturity needed w.r.t. control, strategic-vs-commodity distinction, etc.

5. 5 SRC Review 001004 abk Goal: Improved Design Technology Productivity u The GSRC C.A.D. Theme promotes mature, coopetitive cultures and shared, open infrastructures that lead to improved creation of design technology u Improved vision and design technology planning (“specify”): s What will the design problem look like? What do we need to solve? u Improved execution (“develop”): s How can we quickly develop the right design technology (TTM)? u Improved measurement (“measure and improve”): s Did we solve the problem (QOR)? Did the design process improve? Did we increase the envelope of achievable design?

6. 6 SRC Review 001004 abk “A Vision of the Future” u Improved vision and design technology planning (“specify”): t What will the design problem look like? What do we need to solve? s Accurate roadmapping for Design (and Process) Technology (“Living Roadmap”)  1.5x more focused R&D resources   1.5x more focused R&D resources u Improved execution (“develop”): t How can we quickly develop the right design technology (TTM)? s Reusable, commodity, Foundation CAD-IP (+ academic publication standards)  reduce TTM to 2-3 yrs, 2x better leveraged R&D and academic resources, 2x increase in “searched solution space” (mix-and-match flow optimizations)   reduce TTM to 2-3 yrs, 2x better leveraged R&D and academic resources, 2x increase in “searched solution space” (mix-and-match flow optimizations) u Improved measurement (“measure and improve”): t Did we solve the problem (QOR)? Did the design process improve? Did we increase the envelope of achievable design? s Design tool/process metrics, design process instrumentation and CPI  1.5x increase in “searched solution space” (flow and process optimizations)   1.5x increase in “searched solution space” (flow and process optimizations) u Design Technology Productivity improves Design Productivity

7. 7 SRC Review 001004 abk Outline u The Design Technology Gap and the GSRC C.A.D. Theme u On Roadmaps u The GSRC Technology Extrapolation (GTX) System: Toward a Living Roadmap u A Living Roadmap for Semiconductors (and Design)

8. 8 SRC Review 001004 abk What is Roadmapping? (Ideally...) u “Roadmapping drives development of (e.g., CAD) technology”: s System architects, designers, CAD managers use roadmaps to determine t tough problems t risks, … s EDA suppliers use roadmaps to determine t R&D investment t product pipeline s Government and consortia use roadmaps to determine levels of investment u “Roadmaps serve as a guide to the most promising directions, the most critical problems”

9. 9 SRC Review 001004 abk What is a Roadmap? (In reality...) u Self-fulfilling prophecy ? s s Moore’s Law: (Circuits per chip) = 2 (year-1975)/1.5 (Gordon Moore, 1975 IEDM) s s “More than anything, once something like this gets established, it becomes more or less a self- fulfilling prophecy. The Semiconductor Industry Association puts out a technology road map, which continues this generation [turnover] every three years. Everyone in the industry recognizes that if you don't stay on essentially that curve they will fall behind. So it sort of drives itself.” (Gordon Moore, 1996) u Always wrong, yet comprised of meta-laws ? s s Reasons for Moore’s Law (1975): die size growth, feature size decrease, circuit/device cleverness s s Gordon Moore, 1975: "There is no room left to squeeze anything out by being clever. Going forward from here we have to depend on the two size factors - bigger dice and finer dimensions.” (Gordon Moore, 1995) u Geopoliticoeconomic ? s s QUIZ: Rank the following four regions by decreasing order of aggressiveness in feature size: United States, Japan, Europe, East Asia

10. 10 SRC Review 001004 abk What is a Roadmap? (In reality...) u Sensitive s s Example 1: Cell Area Factor for memory   Scenario 1: 8x/1999  2.5x/2014   Scenario 2: 8x/1999  4x/2016 s s Example 2: Litho Field Size Maximum Limit   Scenario 1: 4x magnification, 6-inch reticle (800mm 2 intro, 400 mm 2 production) t t Scenario 2: 5x magnification, 6-inch reticle (572mm 2 intro, 286 mm 2 production) s s Example 3: L2 Cache Size for High-Perf MPU (baseline of ramp going forward)   Scenario 1: 2MB on-chip 6t SRAM  170mm 2 core + 280mm 2 SRAM = 450mm 2 in 1999   Scenario 2: 1MB on-chip 6t SRAM  170mm 2 core + 140mm 2 SRAM = 310mm 2 in 1999 s s QUIZ: By what factor will the high-performance MPU transistor count at the end of the Roadmap change if we switch between Scenario 1 and Scenario 2 ?

11. 11 SRC Review 001004 abk What is a Roadmap? (In reality...) u Always evolving s In: gate length “in resist” vs. “physical”, CMP dishing, SOC complexity,... s Out: NRE cost of logic (including design cost!),... s In flux : “in volume production”, “no known solution”, “high-perf MPU”,... u Conflicted between Forecasts vs. Statements of Needs s s “a statement of technology needs in various areas, driven by a forecast of lithography capability” (D. Jensen, AMD) s s “a hybrid of the ‘most realistic aggressive’ targets, balanced by the tension created by the ‘red’ limits of ‘unknown solutions’” (A. Allan, Intel) u u Paralyzed by dependencies s s “who owns #package pins/balls?” Test? Assembly/Packaging? Design? s s how does one go about changing a number, checking for interactions ? u u Law of Roadmaps: If it’s worth roadmapping, it can’t be roadmapped.

12. 12 SRC Review 001004 abk 1994 1997 1998/1999 500 350 250 180 130 100 70 50 35 25 DRAM Half Pitch MPU/ASIC Gate “Physical” MPU/ASIC Gate “In Resist” 90 65 45 33 23 ~.7x per technology node (.5x per 2 nodes) Year of Production and MPU/ASIC Gate Length Minimum Feature Size (nm) Technology Node - DRAM Half-Pitch (nm) Technology Node Minimum Feature [1.0] [1.5] [2.0] Scenarios: 16 959799010407101316 959799010407101316 ITRS Acceleration

13. 13 SRC Review 001004 abk What Should a Roadmap Be? (More Practically...) u Comprehensive and “best possible” u Robust u Flexible and adaptive u “A Living Roadmap” ???

14. 14 SRC Review 001004 abk Outline u The Design Technology Gap and the GSRC C.A.D. Theme u On Roadmaps u The GSRC Technology Extrapolation (GTX) System: Toward a Living Roadmap u A Living Roadmap for Semiconductors (and Design)

15. 15 SRC Review 001004 abk Technology Extrapolation u Evaluates impact of s design technology s process technology u Evaluates impact on s achievable design s associated design problems u What do we need to solve? u What will the design problem look like ? u == Roadmapping to drive Design Technology How and when do L, SOI, SER, etc. matter? What is the most power-efficient noise management strategy? Will layout tools need to perform process simulation to effectively model cross-die and cross-wafer manufacturing variation?

16. 16 SRC Review 001004 abk u Most commonly used optimal repeater sizing expression (Bakoglu) u New study: s Sweep repeater size for single stage in the chain s Examine both delay and energy-delay product Optimal Repeater Sizing 0100200300400500 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 Bakoglu optimal sizing L seg = 2.14 mm W=S=1  m W=S=0.5  m Critical Path Delay (ns) Repeater Size (X min size) 1 2 3 4 5 6 Normalized Energy-Delay Product

17. 17 SRC Review 001004 abk Elastic scattering Diffuse scattering Effect of Electron Scattering Effect of 5 nm Barrier Conformal 5 nm barrier assumed Even a 5 nm barrier will increase resistivity drastically No barrier assumed Electron scattering increases resistivity Lowering temperature has a big effect 525 320 250 95 58 48 280 170 133 ITRS 1999 Line width (nm) Global Semiglobal Local source: MARCO IFRC Cu Resistivity: Effect of Line Width Scaling

18. 18 SRC Review 001004 abk Technology Extrapolation Today u Many Roadmaps s ITRS, JISSO, STARC, … Roadmaps s University tools: SUSPENS, GENESYS, RIPE, BACPAC, … s Industry tools: HIVE/AIM,... u Observations s everyone predicts “same” parameters but different assumptions, inputs: near-total duplication of effort !!! s no documentation or visibility into internal calculations s “hard-wired”  cannot easily test other modeling choices s missing: models of CAD tools and optimizations (what is really “achievable”?) s missing: scope, comprehensive coverage

19. 19 SRC Review 001004 abk u Flexibility s edit or define new parameters and relations between them s perform specific studies (but different studies at different times) u Quality s continuous improvements s world-wide participation of experts u Transparency s open-source mechanism s models visible to the user u No more redundant effort s permanent repository of first choice s adoptability and maintainability A Shared Technology Extrapolation System

20. 20 SRC Review 001004 abk GTX: GSRC Technology Extrapolation System u GTX = framework for shared technology extrapolation u “Living Roadmap”: Repository, sanity-checker for 2001 ITRS renewal (via US Design TWG, (inter-) ITWG activity) u Open-source: http://vlsicad.cs.ucla.edu/GSRC/GTX/ Parameters (data) Rules (models) Rule chain (study) Knowledge Engine (derivation) GUI (presentation) Implementation User inputs Pre-packaged GTX

21. 21 SRC Review 001004 abk Knowledge Representation u Human-readable ASCII grammar #rule BACPAC_dl_chip #description#output double {m} dl_chip; #inputs double {m^2} dA_chip; #body sqrt(dA_chip) #reference#endrule #parameter dl_chip #type double #units {m} #default1e-2#description chip side length #reference#endparameter

22. 22 SRC Review 001004 abk Knowledge Representation u Human-readable ASCII grammar u Benefits: s Easy creation/sharing of parameters/rules by multiple users t D. Sylvester and Y. Cao: device and power, SOI modules that “drop in” to GTX t P.K. Nag: Yield modeling s Extensible to models of arbitrary complexity (specialized prediction methods, technology data sets, optimization engines) t Avant! Apollo or Cadence SE P&R tool: just another wirelength estimator s Applies to any domain of work in semiconductors, VLSI CAD t Transistor sizing, single wire optimizations, system-level wiring predictions,…

23. 23 SRC Review 001004 abk Parameters u Description of technology, circuit and design attributes u Importance of consistent naming cannot be overstated s Naming conventions for parameters [ ] _ _ {[qualifier] _ } _ { } _ [ ] _ [ ] _ [ ]  Example: r_int_tot_lyr_pu_dl s Requirements: t Relatively easy to understand parameter from its name t Distinguishable (no two parameters should have the same name) u r_int (interconnect resistance) = r_int (interconnect resistivity) ? t Unique (no two names for the same parameter) u R_int = R_wire ? t Sortable (important literals come first) s Software to automatically check parameter naming

24. 24 SRC Review 001004 abk Rules u Methods to derive unknown from known parameters u ASCII rules s Laws of physics, models of electrical behavior, statistical models s Include closed-form expressions, vector operations, tables s Storing of calibration data (e.g., “technology files”) for known process and design points in lookup tables s Constraints, u sed to limit range during “sweeping” u “External executable” rules s Assume a callable executable (e.g., PERL script) s Use command-line interface and transfer through files s Allow complex semantics of a rule u “Code” rules s Implemented in C++ and linked into the inference engine

25. 25 SRC Review 001004 abk Rule Chains u “Rule chains” guide inference s Acyclic set of rules s Interactive specification and comparison of alternative modeling choices u Studies s Input values + rules that make a rule chain s User-controlled and savable s “Sweeping” of a rule chain t Evaluation of all combinations of multi-valued inputs t Example: clock frequency for different Rent exponents and varying logic depth

26. 26 SRC Review 001004 abk GTX Engine u Contains no domain-specific knowledge u Evaluates rules in topological order u Performs studies u Multiple values through “sweeping” u Runs on three platforms (Solaris, Windows and Linux) u URL: http://vlsicad.cs.ucla.edu/GSRC/GTX/ Parameters (data) Rules (models) Rule chain (study) Knowledge Engine (derivation) GUI (presentation) Implementation User inputs Pre-packaged GTX

27. 27 SRC Review 001004 abk Graphical User Interface (GUI) u Provides user interaction u Visualization (plotting, printing, saving to file) u 4 views: s Parameters s Rules s Rule chain s Values in chain

28. 28 SRC Review 001004 abk u Change parameter values and observe resulting difference in outputs Sensitivity Analysis of Cycle-time Models: Parameter Sensitivity

29. 29 SRC Review 001004 abk Sensitivity Analysis of Cycle-time Models: Model Sensitivity u Replace rule in a model’s rule chain by another model’s rule and observe the difference in outputs BACPAC BACPAC with rule from Fisher

30. 30 SRC Review 001004 abk u Staggered repeaters s Introduced in [Kahng et al, VLSI Design 99] to reduce delay and noise Delay Uncertainty Study SOI (NS) bulk (NS) SOI (S) bulk (S)

31. 31 SRC Review 001004 abk Outline u The Design Technology Gap and the GSRC C.A.D. Theme u On Roadmapping u The GSRC Technology Extrapolation (GTX) System: Toward a Living Roadmap u A Living Roadmap for Semiconductors (and Design)

32. 32 SRC Review 001004 abk GTX Status u Recent Developments s GTX is multi-platform, open-source (MIT license) t many industry downloads; basis of development project at eSilicon (?) s Third release of GTX: September 3, 2000 t namespaces, partial rule chain evaluation, vector types, etc. s Models/studies implemented: t cost/yield (CMU), SOI device/power (Synopsys/Berkeley), RLC interconnect modeling and optimization (SGI/UCLA/Synopsys/Berkeley/Sun), routability and layer assignment (UCLA/Ghent) s GENESYS, RIPE source code translation into GTX u Near-Term Futures s Functionality: annotations, “intelligence”, more direct Roadmap support s Models/studies: RLC interconnect noise/delay, manufacturing variability, clock distribution, DRAM/logic implementation tradeoffs, packaging tradeoffs, device layout density,... s GTX = repository for ITRS-2001 ORTCs (“transparent, living Roadmap”)

33. 33 SRC Review 001004 abk Roadmapping Challenges u u Valuation, evaluation of Design and Design Technology s s scope and definition of design technology, design processes ? s s formal metrics for QOR, effectiveness of design technology ? s s cost measures for design ? (e.g., as part of semiconductor NRE $) u u Real linkage between Design, other TWGs in ITRS-2001 effort s s Test, Interconnect, Litho, PIDS, FEP, Assembly/Packaging,... s s goal: consistency and integrity of ITRS u u Contributions from across the semiconductor process and design communities s s best known methods and models; best known data

34. 34 SRC Review 001004 abk u The GSRC C.A.D. Theme promotes mature, coopetitive cultures and shared, open infrastructures that lead to improved creation of design technology (see: http://vlsicad.cs.ucla.edu/GSRC/ ) u Improved vision and design technology planning (“specify”): s What will the design problem look like? What do we need to solve? s Answer: “Living Roadmap” (The GSRC Technology Extrapolation (GTX) System) u Improved execution (“develop”): s How can we quickly develop the right design technology (TTM)? s Answer: CAD-IP Reuse (The GSRC Bookshelf for Fundamental CAD-IP) u Improved measurement (“measure and improve”): s Did we solve the problem (QOR)? Did the design process improve? Did we increase the envelope of achievable design? s Answer: Design Process Instrumentation, Optimization (METRICS) Toward Improved Design Technology Productivity

35. 35 SRC Review 001004 abk u U.S. Design Technical Working Group for ITRS-2001 renewal s structure, scope, content, links for Design, System Drivers chapters u IEEE DATC Electronic Design Processes Subcommittee s edps-all@eda.org ; EDP Workshop (April, Monterey CA) u MARCO GSRC C.A.D. Theme s Bookshelf for CAD-IP Reuse, METRICS Initiative s http://vlsicad.cs.ucla.edu/GSRC/ u GTX s new models and studies ; usability, use model feedback u My contact info: abk@ucsd.edu Make Your Contribution !!!

36. 36 SRC Review 001004 abk “The Design Productivity Gap” Equivalent Added Complexity 68 %/Yr compounded Complexity growth rate 21 %/Yr compound Productivity growth rate Year Technology Chip Complexity Frequency Staff Staff Cost* 3 Yr. Design 1997 250 nm 13 M Tr. 400 MHz 210 90 M 1998 250 nm 20 M Tr. 500 270 120 M 1999 180 nm 32 M Tr. 600 360 160 M 2002 130 nm 130 M Tr. 800 800 360 M * @ $ 150 k / Staff Yr. (In 1997 Dollars) Logic Tr./Chip Tr./S.M. “How many gates can I get for $N?” Source: SEMATECH $1 $3 $10 Potential Design Complexity and Designer Productivity

37. 37 SRC Review 001004 abk Percent of die area that must be occupied by memory to maintain SOC design productivity Design Productivity Gap  Low-Value Designs? Source = Japanese system-LSI industry

38. 38 SRC Review 001004 abk “Roadmap Process and Its Implications” (Ideally...) Basic Technological Assumptions Basic Methodological Assumptions Implications to the Community Models and Discussion Translation to Specific Research Agendas “Timing closure is a hard problem and will only get harder” “We will fund research on timing-aware partitioning” Research Proposed to Implement Agenda R. Newton, ICCAD99 panel

39. 39 SRC Review 001004 abk “Roadmap Process” (More Practically...) Basic Technological Assumptions Basic Methodological Assumptions Implications to the Community Models and Discussion Couched in Terms of Roadmap Implications “Timing closure is a hard problem and will only get harder” Research Proposed to Solve Hard Problem “I can make a breakthrough in technology or methodology” “Here’s how my work is critical for addressing your problem” New models R. Newton, ICCAD99 panel

40. 40 SRC Review 001004 abk u Five different interconnect models s Bakoglu’s model (RC) s [Alpert, Devgan and Kashyap, ISPD 2000] (RC) s [Ismail, Friedman and Neves, TCAD 19(1), 2000] (RLC) s [Kahng and Muddu, TCAD 1997] (RLC) s Extension of [Alpert, Devgan and Kashyap, ISPD 2000] (RLC) RLC Interconnect Delay Approximation 25 75 125 175 225 3.04.05.06.07.08.09.010.0 Wire Length (mm) Wire Delay (ps) RC_ADK RC_B RLC_ADK RLC_IFN RLC_KM HSPICE 25 45 65 85 105 125 145 0.40.60.81.01.21.4 Wire Width (µm) Wire Delay (ps) RC_ADK RC_B RLC_ADK RLC_IFN RLC_KM HSPICE

41. 41 SRC Review 001004 abk Cu Resistivity: Barrier Deposition Technology Atomic Layer Deposition (ALD) Ionized PVD Collimated PVD 5 nm barrier assumed at the thinnest spot No scattering assumed, I.e., bulk resistivity Interconnect dimensions scaled according to ITRS 1999 source: MARCO IFRC