1. Idongesit Ebong (1-1) Jenna Fu (1-2) Bowei Gai (1-3) Syed Hussain (1-4) Jonathan Lee (1-5) Design Manager: Myron Kwai Overall Project Objective: Design a chip as part of a system that accommodates the growing demand for radio frequency identification (RFID) technology while creating a quicker, more convenient shopping experience. Presentation #9: Smart Cart 525 Stage IX: 16 Mar. 2005 Chip Level Layout

2. Status Design Proposal Project chosen Verilog obtained/modified Architecture Proposal Behavioral Verilog simulated Size estimates/floorplanning Gate-level implementation simulated in Verilog Floorplan and more accurate transistor count Schematic Design Component Layout Functional Block Layout DRC of functional blocks LVS of functional blocks Chip Level Layout (98.56% Done) 3 Main blocks (each block LVSes) Full chip LVS  Simulations

3. Design Decisions Decided to route more wires over the SBOX and use metal 4 to reach registers on the right Move items in the encryption block higher up and redesign SBOX logic

4. Previously…

5. Currently (320.220x293.355)

6. Updated Transistor Count OldNew Encryption13,05413,904 Multiplier20422126 Adder544600 SRAM2276 Logic400594 Registers (inputs/outputs)2540 Total20,85622,040

7. Updated Floorplan Area:Old (μm 2 )New (μm 2 ) Encryption68,35260,983 Multiplier88568420 Adder39203429 SRAM10,6958183 Logic/Wiring14,655 Registers (inputs/outputs, counters)44904266 Total110,96891,365 Density: ( transistors/μm 2 ) Aspect ratio:.19 1.36 0.26 1.1

8. Layer Masks Poly

9. Layer Masks Metal1

10. Layer Masks Metal2

11. Layer Masks Metal3

12. Layer Masks Metal4

13. Layout: Multiplier

14. Layout: SRAM/Adder

15. Layout: FinalText/Initial Permutation

16. Layout: Mix Column/Rcon

17. Layout: Key Expand

18. Layout: SBOX

19. Problems & Questions Registers problematic How can we make the chip smaller? Re-doing many of the blocks, learn from previous mistakes. Reset signal strength and buffer size needed for it. White space reduction Simulations take a long time.