1. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 1 Digital Integrated Circuits A Design Perspective Designing Combinational Logic Circuits Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić November 2002.

2. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 2 Issues in Dynamic Design 1: Charge Leakage CLCL Clk Out A MpMp MeMe Leakage sources CLK V Out Precharge Evaluate Dominant component is subthreshold current

3. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 3 Solution to Charge Leakage CLCL Clk MeMe MpMp A B Out M kp Same approach as level restorer for pass-transistor logic Keeper

4. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 4 Issues in Dynamic Design 2: Charge Sharing CLCL Clk CACA CBCB B=0 A Out MpMp MeMe Charge stored originally on C L is redistributed (shared) over C L and C A leading to reduced robustness

5. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 5 Charge Sharing CLCL Clk CACA B=0 A V Out VXVX Slide by Kia

6. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 6 Charge Sharing CLCL Clk CACA B=0 A V Out VXVX Slide by Kia

7. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 7 Charge Sharing B  0 Clk X C L C a C b A Out M p M a V DD M b Clk M e

8. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 8 Solution to Charge Redistribution Clk MeMe MpMp A B Out M kp Clk Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

9. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 9 Issues in Dynamic Design 3: Backgate Coupling C L1 Clk B=0 A=0 Out1 MpMp MeMe Out2 C L2 In Dynamic NANDStatic NAND =1 =0

10. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 10 Backgate Coupling Effect Voltage Time, ns Clk In Out1 Out2

11. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 11 Issues in Dynamic Design 4: Clock Feedthrough CLCL Clk B A Out MpMp MeMe Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above V DD. The fast rising (and falling edges) of the clock couple to Out.

12. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 12 Clock Feedthrough Clk In 1 In 2 In 3 In 4 Out In & Clk Out Time, ns Voltage Clock feedthrough

13. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 13 Other Effects  Capacitive coupling  Substrate coupling  Minority charge injection  Supply noise (ground bounce)

14. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 14 Cascading Dynamic Gates Clk Out1 In MpMp MeMe MpMp MeMe Clk Out2 V t ClkIn Out1 Out2 VV V Tn Only 0  1 transitions allowed at inputs!

15. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 15 Domino Logic In 1 In 2 PDN In 3 MeMe MpMp Clk Out1 In 4 PDN In 5 MeMe MpMp Clk Out2 M kp 1  1 1  0 0  0 0  1

16. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 16 Properties of Domino Logic  Only non-inverting logic can be implemented  Very high speed  static inverter can be skewed, only L-H transition  Input capacitance reduced – smaller logical effort  Better noise margin

17. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 17 Why Call it Domino? Clk In i PDN In j In i In j PDN In i PDN In j In i PDN In j Like falling dominos!

18. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 18 Footer needed? Clk Out1 In Clk Out2 Slide by Kia (fig by Rabaey)

19. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 19 Designing with Domino Logic M p M e V DD PDN Clk In 1 2 3 Out1 Clk M p M e V DD PDN Clk In 4 Clk Out2 M r V DD Inputs = 0 during precharge Can be eliminated!

20. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 20 Footless Domino The first gate in the chain needs a foot switch Precharge is rippling – short-circuit current A solution is to delay the clock for each stage

21. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 21 Domino Layout Slide by Kia

22. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 22 np-CMOS In 1 In 2 PDN In 3 MeMe MpMp Clk Out1 In 4 PUN In 5 MeMe MpMp Clk Out2 (to PDN) 1  1 1  0 0  0 0  1 Only 0  1 transitions allowed at inputs of PDN Only 1  0 transitions allowed at inputs of PUN

23. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 23 NORA Logic In 1 In 2 PDN In 3 MeMe MpMp Clk Out1 In 4 PUN In 5 MeMe MpMp Clk Out2 (to PDN) 1  1 1  0 0  0 0  1 to other PDN’s to other PUN’s WARNING: Very sensitive to noise!

24. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 24 Differential (Dual Rail) Domino A B MeMe MpMp Clk Out = AB !A!B M kp Clk Out = AB M kp MpMp Solves the problem of non-inverting logic 1 0 on off

25. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 25 Multiple-Output Domino