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MEMS Cell Adhesion Device Andrea Ho Mark Locascio Owen Loh Lapo Mori December 1, 2006
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PVDF (Piezoelectric) SiO 2 Si Parylene PDMS PLA Top Electrode Bottom Electrodes Via Ni Traces (Layer 2) Ni Traces (Layer 1) Summary of Fabrication Based on passive PDMS pillar arrays Add 3-axis force sensitivity on each pillar Thin membrane over pillars Alignment is critical Pillars, piezoelectric elements, electrodes Use single set of alignment marks for all layers PDMS Membrane [Roure, et al. PNAS 2005]
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1.Si wafer 2.Deposit silicon nitride by LPCVD 3.Spincoat with resist 4.Pattern alignment features in resist 5.Etch silicon nitride using RIE 6.Strip resist in oxygen plasma Fabrication - Alignment Features
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1.Spincoat with resist 2.Pattern resist by e-beam lithography 3.Etch Si using DRIE 4.Strip resist 6.Pour PLA 7.Deposit common top electrode by e-beam evaporation 5.(Silanize wafer to improve PLA release) Fabrication - Pillar Mold
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1.Spincoat with PVDF (piezoelectric) 2.Spincoat with resist 3.Pattern using e-beam lithography 4.Etch PVDF using RIE 5.Strip resist Fabrication - Piezoelectric Elements
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1.Spincoat with PDMS 2.Pattern bottom electrodes and first set of traces by e-beam lithography and liftoff 3.Deposit SiO2 dielectric layer by PECVD 11.Deposit parylene by CVD 4.Spincoat with e-beam resist and pattern by e-beam lithography 5.Etch through SiO2 by RIE 7.Sputter with Ni 8.Spincoat with e-beam resist and pattern by e-beam lithography 9.Etch exposed Ni 6.Strip resist in acetone 10.Strip resist Fabrication - Electrodes Electrodes PVDF
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1.Flip over and bond parylene layer to Si wafer with low heat and pressure 2.Peel off top Si wafer and SU-8 mold Fabrication - Wafer Bonding
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1.Begin with Si wafer 2.Spincoat with photoresist 3.Spincoat with diluted PDMS 4.(Treat in oxygen plasma) PDMS Membrane
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1.Flip over PDMS-coated wafer and bond to pillars 2.Peel away support wafer 3.(Treat in oxygen plasma) Mold Release
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Parametric Study Dependence of output voltage on pillar geometry Diameter Height Electrode geometry material properties
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Parametric Study
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Response
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Inverse analysis
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FEM analysis Model geometryMesh
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FEM results It is reasonable to assume constant z over the piezoelectric material.
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Additional results Resonance frequencyTip displacement
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Frequency Response Lumped element model Long, thin Ni wires in and out of pillar Electrode of pillar modeled as parallel resistor & capacitor R wire R PVDF C PVDF
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Frequency Response Circuit element values calculated from material properties
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Frequency Response Combine impedances Take output across Z P ZwZw ZwZw Z PR Z PC ZwZw ZwZw ZPZP Z EQ
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Frequency Response Bode plot shows ω C >> any frequency we will be sensing
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Thermal Noise The electrodes and PVDF form an RC system As in Senturia, this arrangement will create thermal noise in the system Need to ensure RMS thermal noise << output voltages
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Thermal Noise Consider noisy resistor to be a noiseless resistor an a voltage source R PVDF C PVDF V OUT V NOISE R PVDF C PVDF
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Thermal Noise Calculate noise bandwidth Calculate thermal noise This is acceptable, since our outputs will be hundreds of mV
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Actuation Piezoelectrics allow for both actuation and sensing Electromechanical coupling factor k k PVDF ≈ 0.1 to 0.3 Easy to run in reverse to stimulate cell
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Actuation Applied voltages will have to be roughly 10x the voltage out for a corresponding deflection This puts it at a reasonable value for actuation voltage Actuation would have to be calibrated experimentally
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Sensitivity Analysis Change in voltage output for a given change in force: Slope of linear parametric plots
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Sensitivity Analysis
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Resolution where system noise is the limiting factor
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Sensitivity Analysis Effect of variation in pillar diameter on output voltage ΔV = (30mV/μm)(0.06 μm) = 1.8 mV Diameter varies by ~10nm → Output voltage varies ~mV Resolution affected by fabrication processes
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Sensitivity Analysis Effect of PVDF layer uniformity (4% ) At F = 100nN, ΔV[mV] = 450Δx[μm] This results in an output voltage range of 36 mV ΔF = 36 mV/5.5061 = 6.54 nN
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Sensitivity Analysis Worst case scenario: At F=100nN, output voltage varies over a total range of 20 + 36 + 1.8 mV = 57.8 mV ΔF = 10.50 nN (~10% error) Effect of variation in pillar height DRIE allows pillar height to vary ~μm At F = 100nN, output voltage can range over 20 mV
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Questions
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