1. Reliable Data Storage using Reed Solomon Code Supervised by: Isaschar (Zigi) Walter Performed by: Ilan Rosenfeld, Moshe Karl Spring 2004 Characterization Presentation

2. The Setting Micro Satellite in space receiving high-detail data from input peripherals This data must be reliably stored!

3. Solution An FPGA System-on-Chip that uses an error-correcting code Cosmic radiation causes bit-flips, and therefore valuable information could be lost (every pixel counts!) Weight == money (and we don’t have a lot of that) Extremely high rate of input data requires unique treatment in storage Problems

4. Reed Solomon codes are very commonly used because of their ability to detect and correct maximum errors with great efficiency. Their hardware implementations are also power-saving. A System-on-Chip weighs much less than anti-radiation shielding. Plus, the whole computer and its functionality are implemented as one chip. The Virtex II PRO FPGA has RocketIO ports that will allow a very high rate of data transfer. How is it solved?

5. Memec Design Virtex II Pro Development Kit Hardware Resources Xilinx Virtex II Pro RocketIO comm. ports

6. Software Tools HDL Designer ModelSim Embedded Development Kit

7. Basic Project Function Reed Solomon Encoder Reed Solomon Decoder Storage Device Hi res Hi freq. input data (possibly) corrupted data (hopefully) corrected data

8. Block Diagram PLB Rocket I/O SDRAM Memory Controller PowerPC RS Decoder RS Encoder Storage Camera CPU offload unit

9. First Semester Goals In-depth acquaintance with the development environments Implementing the Reed Solomon coding within one chip, as a slave component on the bus.

10. First Semester Goals – cont. PLB Memory Controller PowerPC RS Decoder RS Encoder SDRAM PLB2OPB Bridge OPB UART DIGLAB PC Controller Buffer

11. First Semester Schedule 4 weeks (done): study the development environments, the Virtex II Pro and PowerPC. Building a tutorial application using the CPU. 1 week: Study the Reed Solomon cores. 1 week: Study the PLB Bus. 2 weeks: Building a test application for connection to the bus. 6 weeks: Designing the described system, simulating, implementing and debugging.

12. Second Semester Goals Building a CPU offload unit that will be a master on the PLB. Using another development board to simulate a storage device. Performing fast and reliable data transfers between the two boards.

13. Second Semester Goal PLB Rocket I/O SDRAM Memory Controller PowerPC RS Decoder RS Encoder Second Development Board (simulating storage device) CPU offload unit PLB2OPB Bridge OPB UART, etc.

14. Thank you