1. 7/2/2015445_23 1 Pipelining ECE-445 Computer Organization Dr. Ron Hayne Electrical and Computer Engineering

2. 7/2/2015 445_232 Pipelining F1F1 E1E1 I1I1 F2F2 E2E2 I2I2 F3F3 E3E3 I3I3 Sequential Execution F1F1 E1E1 I1I1 F2F2 E2E2 I2I2 F3F3 E3E3 I3I3 Pipelined Execution

3. 7/2/2015 445_233 Hardware Organization Instruction Fetch Unit Execution Unit Interstage Buffer B1

4. 7/2/2015 445_234 Four State Pipeline  Fetch (F) Read the instruction from memory  Decode (D) Decode the instruction and fetch the source operand(s)  Execute (E) Perform the operation specified by the instruction  Write (W) Store the result in the destination location

5. 7/2/2015 445_235 Four Stage Pipeline

6. 7/2/2015 445_236 Hardware Organization

7. 7/2/2015 445_237 Data Hazard  Pipeline stalled  Source or destination operands not available at time expected in the pipeline  Execution operation taking more than one clock cycle

8. 7/2/2015 445_238 Data Hazard

9. 7/2/2015 445_239 Data Dependency

10. 7/2/2015 445_2310 Operand Forwarding

11. 7/2/2015 445_2311 Operand Forwarding

12. 7/2/2015 445_2312 Handling Data Hazards in SW  Compiler detect data dependencies and deal with them Insert NOPs Attempt to reorder instructions to perform useful tasks in NOP slots  Side effects Instruction changes contents of a register other than the named destination Autoincrement/autodecrement addressing modes Condition code flags Give rise to multiple dependencies Should be minimized

13. 7/2/2015 445_2313 Instruction Hazards  Pipeline stalled  Delay in the availability of an instruction Cache miss Branch instructions

14. 7/2/2015 445_2314 Instruction Hazard

15. 7/2/2015 445_2315 Instruction Queue and Prefetch

16. 7/2/2015 445_2316 Branch Penalty

17. 7/2/2015 445_2317 Branch Prediction  Attempt to predict whether or not a particular branch will be taken  Speculative execution Continue to execute until outcome of branch evaluated No processor registers or memory can be updated until branch outcome is confirmed

18. 7/2/2015 445_2318 Branch Prediction  Static Branch Prediction Some branch instructions predicted as taken and others as not taken End or program loop Beginning of program loop Hardware or compiler  Dynamic Branch Prediction Based on execution history

19. 7/2/2015 445_2319 Structural Hazard  Two instructions require use of a given hardware resource at the same time Access to memory Separate instruction and data caches Access to register file Multiple port register file  In general avoided by providing sufficient hardware resources on the processor chip

20. 7/2/2015 445_2320 Structural Hazard

21. 7/2/2015 445_2321 Summary  Pipelining does not result in individual instructions being executed faster  Throughput increases Rate at which instruction execution is completed  Important goal in designing processors is to identify all hazards that may cause the pipeline to stall Find ways to minimize their impact

22. 7/2/2015 445_2322 Questions?