1. Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 27: November 5, 2014 Dynamic Logic Midterm 2 Avg: 58 Std Dev.: 15

2. Today Clocking Dynamic (Clocked) Logic –Strategy –Form –Compare CMOS Penn ESE370 Fall2014 -- DeHon 2

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4. Clocking Penn ESE370 Fall2014 -- DeHon 4

5. Two Phase Non-Overlapping Clocks Build master-slave register from pair of latches Control with non-overlapping clocks Penn ESE370 Fall2013 -- DeHon 5

6. Clocking Highlights Clock discipline simplifies logic composition –Abstracts many internal timing details –Just concerned with making clock period long enough Breaking logic up with registers allows to run at high frequency – reuse logic Discipline – keeping data stable around clock edge –Setup, hold time – determined by circuit –Clk  Q delay for data come out of register Penn ESE370 Fall2014 -- DeHon 6

7. Clocking Circuits typically operate in a clocked environment Gives some additional structure we can exploit Penn ESE370 Fall2014 -- DeHon 7

8. Dynamic Logic Penn ESE370 Fall2014 -- DeHon 8

9. Motivation Like to avoid driving pullup/pulldown networks –reduce capacitive load Power, delay Penn ESE370 Fall2014 -- DeHon 9

10. Motivation Like to avoid driving pullup/pulldown networks –reduce capacitive load Power, delay Ratioed had problems with –Large device for ratioing –Slow pullup –Static power Penn ESE370 Fall2014 -- DeHon 10

11. Idea Use clock to disable pullup during evaluation Penn ESE370 Fall2014 -- DeHon 11

12. Discuss Use clock to disable pullup during evaluation What happens when –/Pre=0, A=B=0 –/pre=1, A=B=0? –/pre=1, A=1, B=0? Sizing implication? Concerns? Requirements? Penn ESE370 Fall2014 -- DeHon 12

13. Advantages Large device –Driven by clock, not data/logic –Can pullup quickly w/out putting load on logic Single network –Pulldown –Don’t have to size for ratio with pullup –Swings rail-to-rail Penn ESE370 Fall2014 -- DeHon 13

14. Domino Logic Penn ESE370 Fall2014 -- DeHon 14

15. Domino AND-OR Penn ESE370 Fall2014 -- DeHon 15

16. Domino Everything charged high –After inverter all inputs low Why do we want this? Disabled, waiting for an enabling transition Penn ESE370 Fall2014 -- DeHon 16

17. Requirements Single transition –Once fires, it is done  like domino falling All inputs at 0 during precharge –Precharge to 1 so inversion makes 0 Non-inverting gates http://en.wikipedia.org/wiki/File:Domino_effect.jpg Penn ESE370 Fall2014 -- DeHon 17

18. Domino or4 Penn ESE370 Fall2014 -- DeHon 18

19. Domino Logic Performance –R 0 /2 input Compare to CMOS cases? nor4 or4 nand4 Penn ESE370 Fall2014 -- DeHon 19

20. Dynamic OR4 Precharge time? Driving input –With R 0 /2 Driving inverter and self cap? Output self delay? Penn ESE370 Fall2014 -- DeHon 20

21. CMOS NOR4 Driving input –With R 0 /2 Driving self cap? Penn ESE370 Fall2014 -- DeHon 21

22. CMOS NAND4 Driving input –w/ R 0 /2 Driving self cap? Penn ESE370 Fall2014 -- DeHon 22

23. Issues Noise sensitive Power? Activity? Penn ESE370 Fall2014 -- DeHon 23

24. Discuss (time permit) Avoid inversion? Converting from CMOS? Post-charge Penn ESE370 Fall2014 -- DeHon 24

25. Observe Better (lower) ratio of input capacitance to drive strength Particularly good for –Driving large loads –Large fanin gates Harder to design with –Timing and polarity restrictions –Avoiding noise Especially with today’s high variation tech. Can consume more energy/op Penn ESE370 Fall2014 -- DeHon 25

26. Idea Dynamic/clocked logic –Only build/drive one network –Fast transition propagation –Spend delay (capacitance) on pullup off critical path of logic –More complicated, power Reserve for when most needed Penn ESE370 Fall2014 -- DeHon 26

27. Admin Homework 7 out –…and due on Tuesday Withdraw date Friday Penn ESE370 Fall2014 -- DeHon 27