1. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 6 CPU Design

2. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter Outline CPU SpecificationCPU Specification Very Simple CPUVery Simple CPU Relatively Simple CPURelatively Simple CPU Simple CPU ShortcomingsSimple CPU Shortcomings 8085 Microprocessor8085 Microprocessor

3. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Specifying a CPU Determine its intended applicationsDetermine its intended applications Develop Instruction Set ArchitectureDevelop Instruction Set Architecture Design State DiagramDesign State Diagram

4. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU State Diagram

5. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Instruction Cycle FetchFetch DecodeDecode ExecuteExecute

6. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Very Simple CPU 64 x 8 memory64 x 8 memory –Address pins A[5..0] –Data Pins D[7..0] 8-bit Accumulator8-bit Accumulator

7. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Non-ISA Registers 6-bit Address Register AR6-bit Address Register AR 6-bit Program Counter PC6-bit Program Counter PC 8-bit Data Register DR8-bit Data Register DR 2-bit Instruction Register IR2-bit Instruction Register IR

8. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Fetching Instructions from Memory CPU outputs address on A[5..0]CPU outputs address on A[5..0] Delay for memory to perform its internal operationsDelay for memory to perform its internal operations Read data from memory on D[7..0]Read data from memory on D[7..0]

9. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Fetch States FETCH1: AR  PC

10. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Fetch States FETCH1: AR  PC FETCH2: DR  M

11. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Fetch States FETCH1: AR  PC FETCH2: DR  M, PC  PC + 1

12. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Fetch States FETCH1: AR  PC FETCH2: DR  M, PC  PC + 1 FETCH3: IR  DR[7..6], AR  DR[5..0]

13. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Fetch State Diagram

14. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Decoding Instructions

15. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Executing Instructions - ADD ADD1: DR  M ADD2: AC  AC + DR

16. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Executing Instructions - AND AND1: DR  M AND2: AC  AC ^ DR

17. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Executing Instructions - JMP JMP1: PC  DR[5..0]

18. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Executing Instructions - INC INC1: AC  AC + 1

19. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Very Simple CPU Specification FETCH1: AR  PC FETCH2: DR  M, PC  PC + 1 FETCH3: IR  DR[7..6], AR  DR[5..0] ADD1: DR  M ADD2: AC  AC + DR AND1: DR  M AND2: AC  AC ^ DR JMP1: PC  DR[5..0] INC1: AC  AC + 1

20. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Very Simple CPU State Diagram

21. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Establishing Data Paths Regroup operations by destination AR: AR  PC; AR  DR[5..0] PC: PC  PC + 1; PC  DR[5..0] DR: DR  M IR: IR  DR[7..6] AC: AC  AC + DR; AC  AC^DR; AC  AC + 1

22. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Establishing Data Paths Determine functions of each component AR, DR, and IR only load dataAR, DR, and IR only load data PC and AC load and increment dataPC and AC load and increment data

23. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Preliminary Register Section

24. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Optimize Register Section AR only supplies data to memoryAR only supplies data to memory

25. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Optimize Register Section AR only supplies data to memoryAR only supplies data to memory IR only supplies data to control unitIR only supplies data to control unit

26. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Optimize Register Section AR only supplies data to memoryAR only supplies data to memory IR only supplies data to control unitIR only supplies data to control unit AC does not supply data to other registersAC does not supply data to other registers

27. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Optimize Register Section AR only supplies data to memoryAR only supplies data to memory IR only supplies data to control unitIR only supplies data to control unit AC does not supply data to other registersAC does not supply data to other registers Bus is 8-bits wide, but some registers have fewer bitsBus is 8-bits wide, but some registers have fewer bits

28. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Optimize Register Section AR only supplies data to memoryAR only supplies data to memory IR only supplies data to control unitIR only supplies data to control unit AC does not supply data to other registersAC does not supply data to other registers Bus is 8-bits wide, but some registers have fewer bitsBus is 8-bits wide, but some registers have fewer bits ALU needed to generate resultsALU needed to generate results

29. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Final Register Section

30. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Very Simple ALU

31. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Generic Hardwired Control Unit

32. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Design Heuristics Assign FETCH1 to counter value 0Assign FETCH1 to counter value 0

33. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Design Heuristics Assign FETCH1 to counter value 0Assign FETCH1 to counter value 0 Assign sequential states to sequential valuesAssign sequential states to sequential values

34. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Design Heuristics Assign FETCH1 to counter value 0Assign FETCH1 to counter value 0 Assign sequential states to sequential valuesAssign sequential states to sequential values Optimize assignment of values to first states of execute routinesOptimize assignment of values to first states of execute routines

35. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 State Assignments Instruction First State IR ADDADD100 ANDAND101 JMPJMP110 INCINC111

36. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Instruction First State IR Counter Value ADDADD1001000 (8) ANDAND1011010 (10) JMPJMP1101100 (12) INCINC1111110 (14) State Assignments

37. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Very Simple CPU Control Unit

38. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Signals

39. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Design Verification 0: ADD4 1: AND5 2: INC 3: JMP 0 4: 27H 5: 39H

40. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Relatively Simple CPU 64K x 8 memory64K x 8 memory –Address pins A[15..0] –Data Pins D[7..0] 8-bit Accumulator AC8-bit Accumulator AC 8-bit General Purpose Register R8-bit General Purpose Register R 1-bit Flag Register Z1-bit Flag Register Z

41. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Instruction Set

42. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Non-ISA Registers 16-bit Address Register AR16-bit Address Register AR 16-bit Program Counter PC16-bit Program Counter PC 8-bit Data Register DR8-bit Data Register DR 8-bit Instruction Register IR8-bit Instruction Register IR 8-bit Temporary Register TR8-bit Temporary Register TR

43. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Fetch Cycle FETCH1: AR  PC FETCH2: DR  M, PC  PC + 1 FETCH3: IR  DR, AR  PC

44. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Fetch and Decode Cycles

45. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 NOP Execute Cycle NOP1: (no operation)

46. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 LDAC Execute Cycle LDAC1: DR  M, PC  PC + 1, AR  AR + 1

47. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 LDAC Execute Cycle LDAC1: DR  M, PC  PC + 1, AR  AR + 1 LDAC2: TR  DR, DR  M, PC  PC + 1

48. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 LDAC Execute Cycle LDAC1: DR  M, PC  PC + 1, AR  AR + 1 LDAC2: TR  DR, DR  M, PC  PC + 1 LDAC3: AR  DR,TR

49. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 LDAC Execute Cycle LDAC1: DR  M, PC  PC + 1, AR  AR + 1 LDAC2: TR  DR, DR  M, PC  PC + 1 LDAC3: AR  DR,TR LDAC4: DR  M

50. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 LDAC Execute Cycle LDAC1: DR  M, PC  PC + 1, AR  AR + 1 LDAC2: TR  DR, DR  M, PC  PC + 1 LDAC3: AR  DR,TR LDAC4: DR  M LDAC5: AC  DR

51. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 STAC Execute Cycle STAC1: DR  M, PC  PC + 1, AR  AR + 1 STAC2: TR  DR, DR  M, PC  PC + 1 STAC3: AR  DR,TR

52. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 STAC Execute Cycle STAC1: DR  M, PC  PC + 1, AR  AR + 1 STAC2: TR  DR, DR  M, PC  PC + 1 STAC3: AR  DR,TR STAC4: DR  AC

53. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 STAC Execute Cycle STAC1: DR  M, PC  PC + 1, AR  AR + 1 STAC2: TR  DR, DR  M, PC  PC + 1 STAC3: AR  DR,TR STAC4: DR  AC STAC5: M  DR

54. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 MVAC and MOVR Execute Cycles MVAC1: R  AC

55. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 MVAC and MOVR Execute Cycles MVAC1: R  AC MOVR1: AC  R

56. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 JUMP Execute Cycle JUMP1: DR  M, AR  AR + 1

57. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 JUMP Execute Cycle JUMP1: DR  M, AR  AR + 1 JUMP2: TR  DR, DR  M

58. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 JUMP Execute Cycle JUMP1: DR  M, AR  AR + 1 JUMP2: TR  DR, DR  M JUMP3: PC  DR,TR

59. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 JMPZ Execute Cycles JMPZY: Jump is takenJMPZY: Jump is taken

60. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 JMPZ Execute Cycles JMPZY: Jump is takenJMPZY: Jump is taken JMPZY1: DR  M, AR  AR + 1 JMPZY2: TR  DR, DR  M JMPZY3: PC  DR,TR

61. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 JMPZ Execute Cycles JMPZY: Jump is takenJMPZY: Jump is taken JMPZY1: DR  M, AR  AR + 1 JMPZY2: TR  DR, DR  M JMPZY3: PC  DR,TR JMPZN: Jump is not takenJMPZN: Jump is not taken

62. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 JMPZY: Jump is takenJMPZY: Jump is taken JMPZY1: DR  M, AR  AR + 1 JMPZY2: TR  DR, DR  M JMPZY3: PC  DR,TR JMPZN: Jump is not takenJMPZN: Jump is not taken JMPZN1: PC  PC + 1 JMPZN2: PC  PC + 1 JMPZ Execute Cycles

63. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 JPNZ Execute Cycles JPNZY: Jump is takenJPNZY: Jump is taken

64. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 JPNZ Execute Cycles JPNZY: Jump is takenJPNZY: Jump is taken JPNZY1: DR  M, AR  AR + 1 JPNZY2: TR  DR, DR  M JPNZY3: PC  DR,TR

65. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 JPNZ Execute Cycles JPNZY: Jump is takenJPNZY: Jump is taken JPNZY1: DR  M, AR  AR + 1 JPNZY2: TR  DR, DR  M JPNZY3: PC  DR,TR JPNZN: Jump is not takenJPNZN: Jump is not taken

66. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 JPNZ Execute Cycles JPNZY: Jump is takenJPNZY: Jump is taken JPNZY1: DR  M, AR  AR + 1 JPNZY2: TR  DR, DR  M JPNZY3: PC  DR,TR JPNZN: Jump is not takenJPNZN: Jump is not taken JPNZN1: PC  PC + 1 JPNZN2: PC  PC + 1

67. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Register Instructions ADD1: AC  AC + R, IF (AC + R = 0) THEN Z  1 ELSE Z  0

68. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Register Instructions ADD1: AC  AC + R, IF (AC + R = 0) THEN Z  1 ELSE Z  0 SUB1: AC  AC - R, IF (AC - R = 0) THEN Z  1 ELSE Z  0

69. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Register Instructions ADD1: AC  AC + R, IF (AC + R = 0) THEN Z  1 ELSE Z  0 SUB1: AC  AC - R, IF (AC - R = 0) THEN Z  1 ELSE Z  0 INAC1: AC  AC + 1, IF (AC + 1 = 0) THEN Z  1 ELSE Z  0

70. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Register Instructions ADD1: AC  AC + R, IF (AC + R = 0) THEN Z  1 ELSE Z  0 SUB1: AC  AC - R, IF (AC - R = 0) THEN Z  1 ELSE Z  0 INAC1: AC  AC + 1, IF (AC + 1 = 0) THEN Z  1 ELSE Z  0 CLAC1: AC  0, Z  1

71. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Register Instructions AND1: AC  AC ^ R, IF (AC ^ R = 0) THEN Z  1 ELSE Z  0

72. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Register Instructions AND1: AC  AC ^ R, IF (AC ^ R = 0) THEN Z  1 ELSE Z  0 OR1: AC  AC  R, IF (AC  R = 0) THEN Z  1 ELSE Z  0

73. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Register Instructions AND1: AC  AC ^ R, IF (AC ^ R = 0) THEN Z  1 ELSE Z  0 OR1: AC  AC  R, IF (AC  R = 0) THEN Z  1 ELSE Z  0 XOR1: AC  AC  R, IF (AC  R = 0) THEN Z  1 ELSE Z  0

74. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Register Instructions AND1: AC  AC ^ R, IF (AC ^ R = 0) THEN Z  1 ELSE Z  0 OR1: AC  AC  R, IF (AC  R = 0) THEN Z  1 ELSE Z  0 XOR1: AC  AC  R, IF (AC  R = 0) THEN Z  1 ELSE Z  0 NOT1: AC  AC, IF (AC = 0) THEN Z  1 ELSE Z  0

75. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Establishing Data Paths

76. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Register Operations Determine functions of each component AR and PC load and increment dataAR and PC load and increment data DR, IR, R, and TR only load dataDR, IR, R, and TR only load data AC and Z will only load dataAC and Z will only load data

77. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Preliminary Register Section

78. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Optimize Register Section AR and IR do not send data to register busAR and IR do not send data to register bus

79. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Optimize Register Section AR and IR do not send data to register busAR and IR do not send data to register bus Pins D[7..0] are bidirectionalPins D[7..0] are bidirectional

80. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Optimize Register Section AR and IR do not send data to register busAR and IR do not send data to register bus Pins D[7..0] are bidirectionalPins D[7..0] are bidirectional Bus is 16-bits wide, but some registers have fewer bitsBus is 16-bits wide, but some registers have fewer bits

81. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Optimize Register Section AR and IR do not send data to register busAR and IR do not send data to register bus Pins D[7..0] are bidirectionalPins D[7..0] are bidirectional Bus is 16-bits wide, but some registers have fewer bitsBus is 16-bits wide, but some registers have fewer bits Register Z is not connected to anythingRegister Z is not connected to anything

82. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Bidirectional Data Pins

83. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Final Register Section

84. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 ALU Design LDAC5: AC  0 + BUS + 0 MOVR1: AC  0 + BUS + 0 ADD1: AC  AC + BUS + 0 SUB1: AC  AC + BUS’ + 1 INAC1: AC  AC + 0 + 1 CLAC1: AC  0 + 0 + 0

85. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 ALU Design

86. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Generic Hardwired Control Unit

87. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Generating States FETCH1 = T0 FETCH2 = T1 FETCH3 = T2 NOP11 = INOP ^ T3 LDAC1 = ILDAC ^ T3 LDAC2 = ILDAC ^ T4

88. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Counter Control Signals INC = 1 when progressing through sequential statesINC = 1 when progressing through sequential states CLR = 1 when returning to FETCH1CLR = 1 when returning to FETCH1

89. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Signals

90. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 INCLUDE JAVA APPLET ANIMATION HERE

91. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Simple CPUs’ Shortcomings More internal registers and cacheMore internal registers and cache Multiple busesMultiple buses Instruction PipelineInstruction Pipeline Larger Instruction SetLarger Instruction Set

92. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 8085 Microprocessor Internal Organization

93. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Summary CPU SpecificationCPU Specification Very Simple CPUVery Simple CPU Relatively Simple CPURelatively Simple CPU Simple CPU ShortcomingsSimple CPU Shortcomings 8085 Microprocessor8085 Microprocessor