1. Low-voltage techniques Mohammad Sharifkhani

2. Reading Text Book I, Chapter 4 Text Book II, Section 11.7

3. Power, Energy, Speed Speed Energy  Battery lifetime Instantaneous power  Package, cooling If leakage is ignored, P x Tpd is equal to E; independent of Vth and Speed: work at the slowest speed; lowest VDD to minimize E (and P).

5. Efficient design approaches

7. Power, Energy, Speed Both Energy and Speed are important: –Energy x Delay is the right index (?) To minimize power –Lower VDD (quadratic dependence, +both leakage and dynamic power) –Reduce C –Lower pt Lower VDD  Delay  4 possibilities –Dual Vth (low Vth only for critical path) –Multiple VDD (low VDD for non critical path) –Parallel, pipeline arch. –Lower Vth to recover the speed

8. VDD scaling

11. VDD scaling vs. delay

12. Processing options

13. Architecture Trade-off for Fixed-rate Processing Reference Datapath

14. Parallel data path

15. Pipeline data path

16. Comparison

19. Multiple supply issues Still on!  DC current

20. Block level voltage scaling

21. Block level multiple supply voltage

22. Multiple VDDs

23. Optimum V2/V1 is around 0.7V Hamada, CICC’01

24. Multiple supply voltages Two supply voltages per block are optimal Optimal ratio between the supply voltages is 0.7 Level conversion is performed on the voltage boundary, using a level-converting flip-flop (LCFF) An option is to use an asynchronous (combinatorial) level converter –More sensitive to coupling and supply noise

25. Level converting FF

28. Shimazaki, ISSCC’03

31. V DDH drives

36. Inverse discrete cosine

48. Delay sensitivity

49. VDD temporal variation Design for Dynamically Varying VDD Ring oscillator. static logic Dynamic logic (& tri-state busses). Sense amp (& memory cell). Max. allowed |dVDD/dt| → Min. CDD = 100nF (0.6μm) Circuits continue to properly operate as VDD changes t VDD

50. Static CMOS

51. Ring oscillator

52. Dynamic Logic

53. Measurement results Dhrystone is a synthetic computing benchmark program developed in 1984 by Reinhold P. Weicker intended to be representative of system (integer) programming. The Dhrystone grew to become representative of general processor (CPU) performance until it was superseded by the CPU89 benchmark

55. Low VDD, Low Vth Rectangle: design variation (VDD and Vth) –Normalized variation on the sides of rectangle when R slides Slide over Eq. Speed lines –Lower power  High power –Power is minimum where P leakage is 10% of the total

56. Low VDD, Low Vth Turn around the axis –Conv.: P α 1/Delay Given VDD and Vth –Opt. : Quadratic Relationship Tune VDD and Vth KEY: Variation of VDD and Vth according to the speed requirements

57. 3 Challenges High standby current in low Vth IDDQ testing failure Degradation of worst case speed due to Vth variation @ low Vth –Vth scaling to keep delay constant: for 3V => 2V change 25% Vth reduction is needed