1. © Copyright 2014 Xilinx. Zynq intr – part 2

2. © Copyright 2014 Xilinx. Description of the interrupt between PL to PS in Vivado 2014.x Content

3. © Copyright 2014 Xilinx. Concat block in 2014.x The concat block maintains the interrupts order.

4. © Copyright 2014 Xilinx. PS interrupt setup in 2014.x The note attached to the interrupt setup tick box is misleading: It gives an incorrect idea of what is happening See on the next slide for what is actually happening

5. © Copyright 2014 Xilinx. Two auto-generated source files are now of interest: –Dev_processing_system7_0_0.v is a wrapper for –Processing_system7_v5_4_processing_system7.v PS7 source files

6. © Copyright 2014 Xilinx. This is a new parameter introduced in 2014.x. It is assigned a value in Dev_processing_system7_0_0.v and passed to Processing_system7_v5_4_processing_system7.v The parameter value passed is “DIRECT”. C_IRQ_F2P_MODE

7. © Copyright 2014 Xilinx. Generated PS source file in 2014.x The “DIRECT” parameter is now used in mapping the interrupt vector IRQ_F2P to the internal interrupt vector irq_f2p_i

8. © Copyright 2014 Xilinx. An illustration of the interrupt mapping for IRQ_F2P_MODE = DIRECT

9. © Copyright 2014 Xilinx. Summary of interrupt mapping strategy in 2014.x in DIRECT mode.