1. 16.317: Microprocessor System Design I Instructor: Dr. Michael Geiger Spring 2012 Lecture 30: PIC data memory

2. Lecture outline Announcements/reminders  Lab 4 posted, due 4/25  Limited # of PICkits  strongly suggest you work in a group for the last two assignments  PICkits can be checked out from the lab  HW 4 to be posted early next week  No class Monday (Patriots’ Day)  Exam regrade requests due today Lecture outline  Review  Microcontroller basics  PIC introduction  Continue with PIC 7/2/2015 Microprocessors I: Lecture 30 2

3. Review Microcontrollers: CPU integrated with storage, I/O devices Examples Timers/event counters Parallel & serial ports Clock generator Analog to digital converter Benefits: low cost/low power, easy to program Limitations: storage, computational power Introduced PIC 16F684 microcontroller 14 pins—12 multiplexed I/O + power/ground All computations using 2 values use accumulator Harvard memory architecture Memory divided into SFR / GPR Dedicated 8-entry system stack for return addresses (subroutines/interrupts) 7/2/2015 Microprocessors I: Lecture 30 3

4. 4 PIC16F684 Block Diagram 7/2/2015

5. Microprocessors I: Lecture 30 5 Harvard vs Von Neumann Organization of program and data memory 7/2/2015

6. Microprocessors I: Lecture 30 6 Data Memory Map Data memory consists of Special Function Registers (SFR) area General Purpose Registers (GPR) area SFRs control the operation of the device GPRs are area for data storage and scratch pad operations GPRs are at higher address than SFRs in a bank Different PIC microcontrollers may have different number of GPRs 7/2/2015

7. Microprocessors I: Lecture 30 7 Banking Data memory is partitioned into banks In this PIC family, each bank holds 128 bytes (max offset = 7Fh) Processors w/4 banks : 4*128 bytes = 512 bytes Processors w/2 banks : 2*128 bytes = 256 bytes Lower locations of each bank are reserved for SFRs. Above the SFRs are GPRs. Implemented as Static RAM Some “high use” SFRs from bank0 are mirrored in the other banks (e.g., INDF, PCL, STATUS, FSR, PCLATH, INTCON) RP0 and RP1 bits in the STATUS register selects the bank when using direct addressing mode. 7/2/2015

8. Banking (cont.) 14-bit instructions use 7 bits to address a location Memory space is organized in 128Byte banks. PIC 16F684 has two banks - Bank 0 and Bank 1. Bank 1 controls operation of the PIC Example: TRISA determines which bits of Port A are inputs/outputs Bank 0 is used to manipulate the data Example: PORTA holds actual state of I/O port A 7/2/2015 Microprocessors I: Lecture 30 8

9. 9 Special Function Registers (1) W, the working register To move values from one register to another register, the value must pass through the W register. FSR ( 04h,84h,104h,184h ), File Select Register Indirect data memory addressing pointer INDF ( 00h,80h,100h,180h ) accessing INDF accesses the location pointed by IRP+FSR PC, the Program Counter, PCL ( 02h, 82h, 102h, 182h ) and PCLATH ( 0Ah, 8Ah, 10Ah, 18Ah ) 7/2/2015

10. Microprocessors I: Lecture 30 10 Special Function Registers (2) STATUS (03h, 83h, 103h, 183h) IRP: Register bank select bit (indirect addressing) RP1:RP0 – Register bank select bits (direct addressing) NOT_TO: Time Out bit, reset status bit NOT_PD: Power-Down bit, reset status bit Z: Zero bit ~ ZF in x86 DC: Digital Carry bit ~ AF in x86 C: Carry bit ~ CF in x86 (note: for subtraction, borrow is opposite) 7/2/2015

11. Microprocessors I: Lecture 30 11 Direct/Indirect Addressing 7/2/2015

12. Microprocessors I: Lecture 30 12 Direct Addressing Lowest 7 bits of instruction identify a register file address The other two bits of register address come from RP0 and RP1 bits in the STATUS register Example: Bank switching (Note: case of 4 banks) CLRF STATUS ; Clear STATUS register (Bank0) : ; BSF STATUS, RP0 ; Bank1 : ; BCF STATUS, RP0 ; Bank0 : ; MOVLW 0x60; Set RP0 and RP1 in STATUS register, other XORWF STATUS, F; bits unchanged (Bank3) : ; BCF STATUS, RP0 ; Bank2 : ; BCF STATUS, RP1 ; Bank0 7/2/2015

13. Direct addressing examples Assume you are using the PIC 16F684, which has two memory banks What address is being accessed if: STATUS = 60h, instruction = 031Fh? STATUS = 40h, instruction = 1F02h? STATUS = 13h, instruction = 0793h? STATUS = EEh, instruction = 03F1h? 7/2/2015 Microprocessors I: Lecture 30 13

14. Example solution Recall that, in direct addressing Address is 8 bits Lowest 7 bits = lowest 7 bits of instruction 8 th bit = RP0 bit of STATUS = STATUS bit 5 STATUS = 60h, instruction = 031Fh? STATUS = 0110 0000 2 Instruction = 0000 0011 0001 1111 2 Address = 1001 1111 2 = 0x9F STATUS = 40h, instruction = 1F02h? STATUS = 0100 0000 2 Instruction = 0001 1111 0000 0010 2 Address = 0000 0010 2 = 0x02 7/2/2015 Microprocessors I: Lecture 30 14

15. Example solution (cont.) Recall that, in direct addressing Address is 8 bits Lowest 7 bits = lowest 7 bits of instruction 8 th bit = RP0 bit of STATUS = STATUS bit 5 STATUS = 13h, instruction = 0793h? STATUS = 0001 0011 2 Instruction = 0000 0111 1001 0011 2 Address = 0001 0011 2 = 0x13 STATUS = EEh, instruction = 03F1h? STATUS = 1110 1110 2 Instruction = 0000 0011 1111 0001 2 Address = 1111 0001 2 = 0xF1 7/2/2015 Microprocessors I: Lecture 30 15

16. Microprocessors I: Lecture 30 16 Indirect Addressing The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register (FSR). The effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit in STATUS register. Example MOVLW 0x20 ;initialize pointer MOVWF FSR ;to RAM NEXT: CLRF INDF ;clear INDF register INCF FSR,F ;inc pointer BTFSS FSR,4;all done? (to 0x2F) GOTO NEXT ;no clear next CONTINUE : ;yes continue 7/2/2015

17. Microprocessors I: Lecture 30 17 I/O Ports General I/O pins are the simplest of peripherals used to monitor and control other devices. For most ports, the I/O pin’s direction (input or output) is controlled by the data direction register TRISx (x=A,B,C,D,E): a ‘1’ in the TRIS bit corresponds to that pin being an input, while a ‘0’ corresponds to that pin being an output The PORTx register is the latch for the data to be output. Reading PORTx register read the status of the pins, whereas writing to it will write to the port latch. Example: Initializing PORTA (PORTA is an 8-bit port. Each pin is individually configurable as an input or output). bcf STATUS, RP0 ; bank0 bcf STATUS, RP1 clrf PORTA ; initializing PORTA by clearing output data latches bsf STATUS, RP0 ; select bank1 movlw 0xCF ; value used to initialize data direction movwf TRISA ; WHAT BITS OF PORT A ARE INPUTS? (0-3, 6, 7) ; WHAT BITS ARE OUTPUTS? (4, 5) 7/2/2015

18. Next time Continue with discussion of PIC 7/2/2015 Microprocessors I: Lecture 30 18