1. Implementation of a Stored Program Computer
Memory addressing
Machine instructions
Assembly language notation
Addressing formats
ITCS 3181 Logic and Computer Systems B. Wilkinson Slides2.ppt Modification date: March 16, 2015

2. Main memory Set of storage locations holding binary patterns.
Used to hold both machine instructions and data
Instructions: Processor fetches binary encoded machine instructions from memory and performs actions defined, e.g. add two numbers together and put result back in memory.
Data: Needed for the calculation stored in memory.

3. Memory Addressing How many bits in each location?
Each location given a unique address (a binary number starting from zero).
Each “addressable” location holds a fixed number of bits.
Any location can be accessed at high speed in any order (random access memory).
How many bits in each location?

4. Size of memory locations
In the early days of computers (perhaps up to 1970), various sizes existed e.g. 24 bits, 36 bits, 40 bits, etc.
Usually dictated by the number of bits in the instruction.
Currently (and for last 40 years at least), each addressable memory location holds 8 bits (a byte).
Originally convenient for holding ASCII (American Standard Code for Information Interchange) code that represented alphanumeric characters (letters, digits, symbols as found on a keyboard).
More recently Unicode/UTF-8 variable width encoding (1 - 4 bytes) mostly used, see

5. Size of memory locations continued
Eight bits not large enough for encoding machine instructions or most numbers. For more than eight bits, consecutive locations used. Address given by address of first location. 4 8 12
Example
int a, b, c, d;
Declaring variables as integers usually means 32-bit integers.
Suppose the integer variables a, b, c, and d are located at addresses 0, 4, 8, 12.

6. Big endian (big end first) Little endian (little end first)
Early common approach
Found in some current processors
Used in network protocols
Little endian (little end first)
Intel uses little endian (a little easier logic)
Little endian/big endian from Gulliver’s Travels

7. Question
Suppose a compiler uses memory locations starting from location zero to hold the variable x using big endian representation. Specify what would be in these memory locations (in binary) if the program has the statement:
int x = 17;
Memory is byte-addressable (each location holding a byte) and x is a 32-bit number.
Answer 1 2 3
17 =
Address

8. Follow-on question Answer 00010001 00000000
Suppose x is then read from memory by a processor using little endian representation. What value would it get?
Answer 1 2 3
Address
224 20
228 +
Answer

9. Machine Instructions
The operation of an instruction reduced to a very simple form.
Consider a calculation one might write in a high level language:
x = (y + z) / (a - b);
where a, b, x, y, and z are declared as integers.
Unreasonable to provide a specific machine instruction just for this calculation.
Need to break down calculation into a series of simple arithmetic operations.

10. Suppose the variables a, b, x, y, and z are stored by the compiler in memory locations 100, 104, 108, 112, and 116:
temp1 = y + z
temp2 = a - b
x = temp1/temp2
temp1, temp2 could be memory locations but better to use fast internal register storage, see later. Note: integers are stored in registers by the compiler if possible

11. Machine Instructions Each of the steps in the previous example:
temp1 = y + z
temp2 = a - b
x = temp1/temp2
might be encoded into one machine instruction.
Each machine instruction usually only has one operation (+, - etc), possibly two source operands, and a single result.

12. Machine Instruction Encoding
A binary pattern that specifies one operation (usually), the operands used for the operation and where the result should be placed if any.

13. Op-code Encoding
Suppose there were 60 different operations, add subtract, multiply, divide, etc. Six bits would be sufficient (25 <= 60 < 26). Could allocate one pattern for each operation:
Example
op-code
ADD (“ADD”)
SUBTRACT (“SUB”)
MULTIPLY (“MUL”)
DIVIDE (“DIV”)
etc. . .
Sometimes more complex encoding used. Many possibilities.
Pattern of all zeros often reserved for no operation (“no-op”)

14. Specifying the Locations of Operands
First let us assume operands and results in main memory:
Three-Address Format
Note
Order of operands here is with destination first but it could be different depending upon processor.

15. Example:
Addition

16. Machine Instruction
The processor executes machine instructions which are binary patterns. The previous machine instruction might be encoded as:
where in this case, 6 bits in opcode and 32 bits for each address.

17. Assembly Language and Machine Instructions
Much more convenient to use an “assembly language” notation to describe machine instruction rather than actual binary patterns.
Previous machine instruction might be written in assembly language as:
ADD [300], [200], [100]
where [ ] means “contents of memory”, a common notation. ADD is the op-code mnemonic.

18. The 3-(memory) address format has the disadvantages:
Long instruction length
Three memory accesses
and rarely used.

19. Two-Address Format
Operands and results in memory. One operand and result same location
Eliminates one address

20. Example:
ADD [200], [100]

21. Disadvantages: One operand overwritten
Still needs three memory accesses

22. One-Address Format
Only one location allowed for one operand and result, a location within the processor, called an accumulator historically.
Other operand still in main memory, and its address given in instruction:

23. Example
ADD [100]

24. Advantages: Disadvantages: Shorter instruction
Eliminates two memory accesses
Faster accessing location inside processor than memory
Disadvantages:
Only one location for one operand and result
Still needs one memory access

25. Register Format
Have more than one location within processor - set of registers.
If there were 32 registers, say R0 to R31, 5 bits are required in each field to specify the register.
This format sometimes called 1 ½ address format.

26. Example
ADD R1, [100]

27. Register-Register Formats
With registers, can now hold all operands in registers and operate on registers only:
If 2 registers specified
If 3 registers specified

28. Example
ADD R3,R1,R2

29. Zero-Address Format
Possible to eliminate all addresses by using specific locations.
Then only the operation need be specified in the instruction
Usually locations for operands/result are top two locations of a stack (a last-in first-out queue) in memory or implemented with registers within processor.
Stack pointer - a register within processor used to hold the address of the top location.

30. Example
ADD
Zero-address format useful to compilers for producing code for arithmetic expressions (using reverse Polish notation)
Used by Burroughs in their computers in the 1960’s and not widely since (but re-introduced in SUN Java chip).

31. A particular processor will not use all formats.
We have outlined several instruction format possibilities:
3-address (3 memory addresses)
2-address (2 memory addresses)
1-address (1 memory address with an accumulator)
1½ address (one memory address and one register address)
Register (3 registers or 2 registers)
Zero-address (no memory addresses, uses stack and stack pointer)
A particular processor will not use all formats.

32. Examples
Intel 64/IA-32 instruction set processors (continuing early 8086 processor designs)
From an external perspective, 1½ address (register-memory) and register formats.
IBM PowerPC, SUN Sparc processor and other so-called reduced instruction set computers
3-register format for arithmetic and register-memory format for accessing memory operands. More details later.

33. Questions