1. IAY 0600 Digitaalsüsteemide disain FSM Decomposition Synthesis Lab. 6 Alexander Sudnitson Tallinn University of Technology

2. Decomposition motivation 2 Often convenient to realize a sequential circuit as an interconnection of sub-circuits that realize the same terminal behavior A large hardware behavioral description is decomposed into several smaller ones First, decide on how the overall circuit is to be broken up and what function each of the sub-circuits must serve Then, treat each of the sub-circuits as a separate and independent design problem. One goal is to make the synthesis problem more tractable by providing smaller sub-problems that can be solved efficiently. Another goal is to create descriptions that can be synthesized into a structure that meets the design constraints.

3. FSM decomposition problem 3 Commonly, FSM decomposition problem is a task of replacement of given prototype FSM with a network of interconnected and interacting component machines, which has the same terminal behaviour. Hardware behavior description is decomposed into a network of interconnected FSMs targeting optimization by various criteria (performance, measurements, power consumption). FSM inputs outputs 1 2 3 n Sub-FSM 2 Sub-FSM 1 Network of FSMs outputs inputs

4. FSM decomposition approaches  In the past, synthesis focused on quality measures based on area and performance. The continuing decrease in feature size and increase in chip density in recent years have given rise to consider decomposition theory for low power as new dimension of the design process.  A range of decomposition techniques has been proposed for the register transfer level optimization of circuits for low power. Various FSM decomposition techniques can broadly fall into two categories: additive decomposition and multiplicative decomposition. 4

5. (c) Giovanni De Micheli 5 Dynamic power management  Systems and components are:  Designed to deliver peak performance, but …  Not needing peak performance most of the time  Dynamic power management (DPM):  Shut-down idle components  Dynamic voltage scaling (DVS)  Slow-down components, by scaling down frequency and voltage

6. Additive decomposition  The main idea of additive decomposition is that the special “idle” state is added to each of sub-FSMs. Only one of sub-FSMs in the decomposed network is working in a time while all the others are suspended (stay in their “idle or sleeping” states).  The network of interacting sub-FSMs corresponds to a given partition on the set of states of prototype FSM.  The number of blocks in the partition defines number of sub-FSMs in the network.  The number of states of each sub-FSM is equal to the number of states in the corresponded block of partition plus one “idle” state. 6

7. Applet 7

8. 8 Example FSM Present state Next state Input condition Output signalsh s1s1 s1s1 x1x1 y7y7 1 s3s3 ^x 1 - 2 s2s2 s3s3 1y 10 y 11 3 s3s3 s6s6 x7x7 4 s8s8 ^x 7 & x 8 - 5 s2s2 ^x 7 & ^x 8 y 2 y 5 y 10 6 s4s4 s1s1 x 1 & x 3 y 3 y 4 7 s3s3 x 1 & ^x 3 y 1 y 3 y 4 8 s7s7 ^x 1 & x 2 y 3 y 4 9 s4s4 ^x 1 & ^x 2 y1y1 10 s5s5 s4s4 x 4 & x 6 y 6 y 13 11 s5s5 x 4 & ^x 6 y 6 y 13 12 s8s8 ^x 4 y 6 y 8 13 s6s6 s2s2 x5x5 y 10 y 11 14 s3s3 ^x 5 & x 7 y 12 15 s8s8 ^x 5 & ^x 7 y 10 y 11 16 s7s7 s5s5 1y1y1 17 s8s8 s8s8 x6x6 - 18 s5s5 ^x 6 y 9 y 14 19 As an example, we use presented Mealy FSM with S={ s 1, s 2, …, s 8 } - set of states, X={x 1, x 2, …, x 8 } - set of binary input variables (channels), Y= {y 1, y 2, …, y 14 } - set of binary output variables (channels) x1x1 x2x2 x8x8 y1y1 y2y2 y 14

9. 9 FSM description Present state Next state Input conditionOutput signals h s4s4 s1s1 x 1 & x 3 y 3 y 4 7 s3s3 x 1 & ^x 3 y 1 y 3 y 4 8 s7s7 ^x 1 & x 2 y 3 y 4 9 s4s4 ^x 1 & ^x 2 y1y1 10 Present state Next state x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 y 1 y 2 y 3 y 4 … y 13 y 14 h s4s4 s1s1 1 - 1 - - - - -001100000000007 s3s3 1 - 0 - - - - -101100000000008 s7s7 0 1 - - - - - -001100000000009 s4s4 0 0 - - - - - -1000000000000010 Here Input conditions (Boolean functions) presented using cubes. Each cube corresponds to the set of input patterns. x1x1 x2x2 x8x8 y1y1 y2y2 y 14 x3x3 y3y3 y4y4 The search for the next state means the evaluation of the Boolean functions. It is necessary to evaluate which of these functions has value “true” for a given input combination  from {0, 1} 8.

10. Partition 10 A partition of a set S is collection of nonempty and pairwise disjoint subsets of S which exhaust the set S. We can give a diagrammatic representation of partitions. If the set S is represented by an enclosed area on paper, we can draw lines to divide the area into nonoverlapping regions. Each region of the resulting diagram will correspond to a block of partition. Distinct partition of S induce distinct equivalence relation on a set S. Example: S={ s 1, s 2, …, s 8 }  ={ { s 1, s 4, s 7 }, { s 2, s 3, s 6 }, { s 5, s 8 } }

11. Decomposition procedure 11 1)Generation of the initial partition 2)Definition of states in component FSMs 3)Definition of the set of external input variables of component FSM 4)Generation of the set of the set of internal (additional) input variables 5)Definition of the set of output variables of component FSMs 6)Generation of transition and output functions of component FSMs 7)Realization of FSM network.

12. Additive decomposition basics 12 Additive decomposition put network N with n component FSM in accordance to pair (A,  ). The number of component FSM is equal to the number of blocks in the partition . A is a given FSM. As example, we use partition,  = { { s 1, s 4, s 7 }, { s 2, s 3, s 6 }, { s 5, s 8 } } So, in this case there will be three component FSM B 1, B 2 and B 2, since there are three blocks ( B 1, B 2 and B 3 ) in the partition .

13. 413 Decomposition example Present state Next state Input condition Output signalsh s1s1 s1s1 x1x1 y7y7 1 s3s3 ^x 1 -2 s2s2 s3s3 1y 10 y 11 3 s3s3 s6s6 x7x7 4 s8s8 ^x 7 & x 8 -5 s2s2 ^x 7 & ^x 8 y 2 y 5 y 10 6 s4s4 s1s1 x 1 & x 3 y 3 y 4 7 s3s3 x 1 & ^x 3 y 1 y 3 y 4 8 s7s7 ^x 1 & x 2 y 3 y 4 9 s4s4 ^x 1 & ^x 2 y1y1 10 s5s5 s4s4 x 4 & x 6 y 6 y 13 11 s5s5 x 4 & ^x 6 y 6 y 13 12 s8s8 ^x 4 y 6 y 8 13 s6s6 s2s2 x5x5 y 10 y 11 14 s3s3 ^x 5 & x 7 y 12 15 s8s8 ^x 5 & ^x 7 y 10 y 11 16 s7s7 s5s5 1y1y1 17 s8s8 s8s8 x6x6 -18 s5s5 ^x 6 y 9 y 14 19 { { s 1, s 4, s 7 }, { s 2, s 3, s 6 }, { s 5, s 8 } }

14. 414 Decomposition example Present state Next state Input condition Output signalsh s1s1 s1s1 x1x1 y7y7 1 s3s3 ^x 1 -2 s2s2 s3s3 1y 10 y 11 3 s3s3 s6s6 x7x7 4 s8s8 ^x 7 & x 8 -5 s2s2 ^x 7 & ^x 8 y 2 y 5 y 10 6 s4s4 s1s1 x 1 & x 3 y 3 y 4 7 s3s3 x 1 & ^x 3 y 1 y 3 y 4 8 s7s7 ^x 1 & x 2 y 3 y 4 9 s4s4 ^x 1 & ^x 2 y1y1 10 s5s5 s4s4 x 4 & x 6 y 6 y 13 11 s5s5 x 4 & ^x 6 y 6 y 13 12 s8s8 ^x 4 y 6 y 8 13 s6s6 s2s2 x5x5 y 10 y 11 14 s3s3 ^x 5 & x 7 y 12 15 s8s8 ^x 5 & ^x 7 y 10 y 11 16 s7s7 s5s5 1y1y1 17 s8s8 s8s8 x6x6 -18 s5s5 ^x 6 y 9 y 14 19 { { s 1, s 4, s 7 }, { s 2, s 3, s 6 }, { s 5, s 8 } }

15. The set of states of (component) sub-FSM An initial partition of example FSM decomposition is  = { { s 1, s 4, s 7 }, { s 2, s 3, s 6 }, { s 5, s 8 } } Set of states in the m-component FSM is defined as: S m = B m  {a m } B m - is the block of the partition , a m - is the additional state that exists in each component FSM. So, in our example: S 1 = { s 1, s 4, s 7, a 1 } S 2 = { s 2, s 3, s 6, a 2 } S 3 = { s 5, s 8, a 3 } The set of states in the component FSM contains the corresponding block of the partition  plus one additional state a. 15

16. 16 External input variables The set of external input variables of m-component FSM is the set of input variables at all transitions from the states of block B m in the transition table of the prototype FSM A. In our example, with partition { { s 1, s 4, s 7 }, { s 2, s 3, s 6 }, { s 5, s 8 } } corresponding sets of external input variables are X(B 1 ) = { x 1, x 2, x 3 } X(B 2 ) = { x 5, x 7, x 8 } X(B 3 ) = { x 4, x 6 } Present state Input conditionh s1s1 x1x1 1 ^x 1 2 s2s2 13 s3s3 x7x7 4 ^x 7 & x 8 5 ^x 7 & ^x 8 6 s4s4 x 1 & x 3 7 x 1 & ^x 3 8 ^x 1 & x 2 9 ^x 1 & ^x 2 10 s5s5 x 4 & x 6 11 x 4 & ^x 6 12 ^x 4 13 s6s6 x5x5 14 ^x 5 & x 7 15 ^x 5 & ^x 7 16 s7s7 117 s8s8 x6x6 18 ^x 6 19

17. 17 External output variables The set of external output variables of m-component FSM is the set of output variables at all transitions from the states of block B m in the transition table of the prototype FSM A. In our example, with partition { { s 1, s 4, s 7 }, { s 2, s 3, s 6 }, { s 5, s 8 } } corresponding sets of external input variables are In our example: Y(B 1 ) = { y 1, y 3, y 4, y 7 } Y(B 2 ) = { y 2, y 5, y 10, y 11, y 12 } Y(B 3 ) = { y 6, y 8, y 9, y 13, y 14 } Present state Output signalsh s1s1 y7y7 1 -2 s2s2 y 10 y 11 3 s3s3 4 -5 y 2 y 5 y 10 6 s4s4 y 3 y 4 7 y 1 y 3 y 4 8 y 3 y 4 9 y1y1 10 s5s5 y 6 y 13 11 y 6 y 13 12 y 6 y 8 13 s6s6 y 10 y 11 14 y 12 15 y 10 y 11 16 s7s7 y1y1 17 s8s8 -18 y 9 y 14 19

18. 18 Generation of transitions of component FSMs (the first sub-FSM) Present state Next state Input condition Output signalsh s1s1 s1s1 x1x1 y7y7 1 s3s3 ^x 1 - 2 s2s2 s3s3 1y 10 y 11 3 s3s3 s6s6 x7x7 4 s8s8 ^x 7 & x 8 - 5 s2s2 ^x 7 & ^x 8 y 2 y 5 y 10 6 s4s4 s1s1 x 1 & x 3 y 3 y 4 7 s3s3 x 1 & ^x 3 y 1 y 3 y 4 8 s7s7 ^x 1 & x 2 y 3 y 4 9 s4s4 ^x 1 & ^x 2 y1y1 10 s5s5 s4s4 x 4 & x 6 y 6 y 13 11 s5s5 x 4 & ^x 6 y 6 y 13 12 s8s8 ^x 4 y 6 y 8 13 s6s6 s2s2 x5x5 y 10 y 11 14 s3s3 ^x 5 & x 7 y 12 15 s8s8 ^x 5 & ^x 7 y 10 y 11 16 s7s7 s5s5 1y1y1 17 s8s8 s8s8 x6x6 - 18 s5s5 ^x 6 y 9 y 14 19 z4z4 z3z3 z3z3 z5z5 { { s 1, s 4, s 7 }, { s 2, s 3, s 6 }, { s 5, s 8 } }

19. The first sub-FSM 19 B 1 x1x1 z4z4 x2x2 x3x3 y 1 y 3 y 4 y 7 z3z3 z5z5

20. Transition table of the first sub-FSM 20 s4s1s7s5s3s5 B3B3 B2B2 B3B3 B1B1 { { s 1, s 4, s 7 }, { s 2, s 3, s 6 }, { s 5, s 8 } }

21. Transformation of transition from s7 to s5 21 s7s5 Prototype_FSM s7 a1 a3 s5 Sub-FSM_1 Sub-FSM_3 y1, z5 z5 - 1

22. FSM Network 22

23. Component FSM B2 23

24. Component FSM B3 24

25. 25 FSM Stochastic Analysis Given the FSM description and the input probabilities, the probabilistic behavior of a FSM can be studied by regarding its transition structure as a Markov chain. A Markov process is a stochastic process, where the past has no influence on the future. In other words, the future behavior depends only on the current state of the process (a “Markov property”). Markov process is called a Markov chain (MC) if its state space is discrete (either finite or countable). One example of MC is the process of playing a board game, where player's next action is determined entirely by rolling a dice. In order to make a move, one takes into account only the current state of the board. It doesn't really matter how the game progressed to that state. Alternatively, in a card game player's move is motivated not only by the cards he or she currently holds, but also the cards which have already been used during the course of the game. Using steady state probabilities, which are received in the result of such analysis, it is possible to build different kinds of quantitative estimations of FSM’s stochastic behavior.

26. A Case Study: Low-Power Design 26 To demonstrate the use of applets in conjunction with FPGA-based development boards, the procedure of computational kernel extraction and implementation will be considered in Lab. Sequential circuits may have an extremely large number of reachable states, but probabilistic analysis show that during normal operation only a relatively small subset is actually being visited. A power optimization paradigm is based on the concept of computational kernel, a highly optimized logic block, which mimics the steady-state behaviour of the original specification.

27. Probability distribution of the FSM 27 State Steady state probability init00.5000001408 init10.3346775136 init20.0877016376 init40.0584677584 IOwait0.0161290368 read00.0006720432 write00.0006720432 RMACK0.0006720432 WMACK0.0006720432 read10.0003360216 The first step of computational kernel extraction procedure is probabilistic analysis of the FSM. It is seen that FSM “opus”-benchmark spends 83% of its operation time in states “init0” and “init1”.

28. Decomposed FSM network 28 After computational kernel is identified, it should be separated from the rest of the circuit. The applet of additive decomposition is used to divide the original circuit into two alternatively working sub-FSMs.

29. Implementation summary 29 VHDL description for prototype FSM and decomposed network can be generated by decomposition applet. This descriptions are used to implement and verify both designs using FPGA-based development board. XPower Analyzer is a tool for power consumption estimation featured in Xilinx ISE. It is used to evaluate the quality of the decomposed design in comparison with the original. DesignArea (LUTs)Power Consumptions (mW) Original254.65 Decomposed361.85 As it is seen from the table, the dynamic power consumption has been reduced by the factor of 2.5, while area overhead is 44%.