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Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 ECE 491 - Senior Design I Lecture 2 FPGAs & Verilog.

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Presentation on theme: "Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 ECE 491 - Senior Design I Lecture 2 FPGAs & Verilog."— Presentation transcript:

1 Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 491 - Senior Design I Lecture 2 FPGAs & Verilog (for Lab 1) Fall 2008 Handout: “Structural Design with Verilog” - read Sections 1-5

2 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design2 Today’s Outline  Overview: Electronic Design with FPGAs  Basic FPGA Structure  FPGA Tradeoffs  The Spartan-3 FPGA  The Spartan-3 Starter Kit Board  Hardware Description Languages  Quick Verilog Overview  What to do in Lab 1

3 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design3 FPGA Organization - Overview

4 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design4 FPGA Organization (Simplified) CLB SB CLB SB CLB IOB - Input/Output Block IOB SB IOB CLB - Configurable Logic BlockSB - Switch Block Switch

5 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design5 FPGA Tradeoffs  Advantages  Very low development cost  Post-manufacturing changes possible  Powerful functions in a small package  Relatively inexpensive  Disadvantages  Inefficient - unused CLBs are still on device  Much slower than ASICs, Custom ICs  Higher power than ASICs, Custom ICs  More expensive than ASICs, Custom ICs in volume

6 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design6 Spartan-3 Organization

7 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design7 Spartan 3 CLB Structure

8 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design8 Spartan 3 Slice Structure

9 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design9 Spartan-3 XC3S200 Details  24 X 20 = 480 CLBs  12 Block RAMs (18kbits ea.)  12 Multipliers (18bit X 18bit)  Up to 173 User I/O pins

10 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design10 Starter Kit Board - Overview FT256 BGA Package JTAG Connector (for programming)

11 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design11 Starter Kit - Block Diagram

12 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design12 Hardware Description Languages  Verilog  Designed by one person at a startup company  Syntax similar to C  Favored by industrial designers  IEEE Standard 1364 (-1995, -2001, -2005)  VHDL  Designed by committee for the Department of Defense  Syntax similar to Pascal, ADA  Favored by government labs, contractors  IEEE Standard 1076 (-1987, -1993, -2000, -2002, -2004) We’ll use Verilog!

13 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design13 Verilog Overview  Important Points About Verilog  The module construct  Combinational Logic  Parameters  Module Instantiation  Sequential Logic  Finite State Machines

14 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design14 Key Point: Verilog is for Hardware!  Verilog code is not like software!  Hardware is parallel  Software is sequential  Think hardware and write code that describes hardware  Follow coding guidelines to avoid pitfalls Zen Master Lin Chi Yi-Sen (note stick) source: http://thezenfrog.wordpress.com

15 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design15 Verilog Hardware Constructs Combinational Logic Registered Logic General Sequential Logic Finite State Machine (FSM)

16 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design16 Important Points about Verilog (cont’d)  Verilog is based on event-driven simulation  Signal values change at specific time points  Each model: Activates in response to input events Creates output events to represent output changes A B C A B C delay=4 input event output event

17 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design17 Important Points about Verilog (cont’d)  Verilog was designed as a simulation language  Synthesis added as an afterthought  Only a subset of the language supported for synthesis  Synthesis must match simulated behavior  Follow coding guidelines to avoid difficulties Image source: http://oldcarandtruckpictures.com/Amphicar/

18 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design18 Important Points about Verilog (cont’d)  Our focus: the synthesizable subset  Structural Descriptions - module instantiations  Behavioral Descriptions assign - continuous assignments always blocks  But, we’ll use simulation capabilities for verification  initial blocks  tasks (subroutines), system tasks, functions  Delay operator

19 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design19 Verilog module construct  Key building block of language  Interface - input and output ports  Body - specifies contents of "black box" behavior - what it does structure - how it's built from module instances (submodules) Mixed behavior and structure (discouraged)

20 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design20 First Example: Full Adder module fulladder(a, b, cin, sum, cout); input a, b, cin; output sum, cout; assign sum = a ^ b ^ cin; assign cout = a & b | a & cin | b & cin; endmodule Ports Port Declarations Semicolon NO Semicolon Continuous Assignment Statements (Parallel)

21 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design21 Comments about First Example  Module interface: input and output ports  Single bit  Multiple bit - array syntax  Module internals:  Internal connections ( wire ) and variables ( reg )  Continuous assignment statements - assign  Concurrent statements - always  Submodule instantiation (hierarchy)  Digital values: (0, 1, X, Z) Only in simulation

22 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design22 Example: 7-Segment Decoder Part 1 Symbolic Constants Port Declarations Variable (reg) Declaration module seven_seg(data, segments); input [3:0] data; output [6:0] segments; reg [6:0] segments; // Output patterns: abc_defg parameter BLANK= 7'b111_1111; parameter ZERO= 7'b000_0001; parameter ONE = 7'b100_1111; parameter TWO= 7'b001_0010; parameter THREE= 7'b000_0110; parameter FOUR= 7'b100_1100; parameter FIVE= 7'b010_0100; parameter SIX= 7'b010_0000; parameter SEVEN= 7'b000_1111; parameter EIGHT= 7'b000_0000; parameter NINE= 7'b000_0100;

23 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design23 Example: 7-Segment Decoder Part 2 always @(data) case (data) 4'd0: segments = ZERO; 4'd1: segments = ONE; 4'd2: segments = TWO; 4'd3: segments = THREE; 4'd4: segments = FOUR; 4'd5: segments = FIVE; 4'd6: segments = SIX; 4'd7: segments = SEVEN; 4'd8: segments = EIGHT; 4'd9: segments = NINE; default: segments = BLANK; endcase endmodule always Statement (Parallel) Case Statement (Sequential) Procedural assignment statements

24 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design24 Example: Module Instance in “s3board” module s3board( clk, pb_in, sw_in, digit_enable_out, segment_out, segment_dp_out,led_out, rxd_in, txd_out ); input clk; // 50MHz clock from board input [3:0]pb_in; // active-high pushbuttons (BTN3-BTN0) input [7:0] sw_in; // active-high slide switches (SW7-SW0) output [3:0] digit_enable_out; // active-low enable for the four // 7-seg display units (AN3-AN0) output [6:0] segment_out; // active-low segments a (6) - g (0) - // shared between the four displays output segment_dp_out; // active-low segment decimal point - // shared between the four displays output [7:0] led_out; // 8 active-high LEDs (LD7-LD0) input rxd_in; // RS-232 port data in output txd_out; // RS-232 port data out assign segment_dp_out = 1’b1; // turn OFF decimal point seven_seg U_SSEG(.data(sw_in[3:0]),.segments(segment_dp_out) ); endmodule // s3board

25 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design25 Using the S3 Board with Verilog  Top-level module file: s3board.v  Contains declarations for all input & output pins Switches & pushbuttons LEDs and 7-segment displays RS-232 port(s) Not used (currently): PS/2 port, VGA port  Use as a starting point for your design  Constraint file: s3board.ucf  Contains pin assignments for all inputs & outputs  Uncomment pins that you’re going to use (remove “ # ”)  Download these files from Moodle

26 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design26 S3 Board: Seven-Segment Display  Segment signals - active low  Digit enables used to “time multiplex” digits

27 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design27 Lab 1 Goals  Learn about the Spartan-3 Starter Kit Board  Review Combinational Logic Design with Verilog  Learn about Basic FPGA Design with Verilog

28 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design28 What to Do in Lab 1  Download “ s3board.v ” and “ s3board.ucf ”  Run ISE and create a new project  Add “ s3board.v ” and “ s3board.ucf ”  Add Verilog code for a 4-bit adder  Add Verilog code for a 7-segment decoder with hex digits  Connect slide switches to adder inputs  Connect 7-segment decoder to adder output  Connect 7-segment decoder to display LSB  Compile, download, & debug  Create report & upload to Moodle (see rubric)

29 ECE 491 Fall 2008Lecture 2 - FPGA-Based Design29 Lab 1 - Block Diagram

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