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VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language  VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

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Presentation on theme: "VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language  VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade."— Presentation transcript:

1 VHDL

2 What is VHDL? VHDL: VHSIC Hardware Description Language  VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade

3 Entity :- The most basic building block in the design. The uppermost level of the design is the top level entity. Entity is a hardware abstration of the actual hardware device. The entity declaration specifies the name of the entity modeled and lists the interfaces. An entity X, when used in another entity Y, becomes a component for the entity Y. R.H.Khade 3 7/2/2015

4 Entity communicates with other models in its external environment through port signals. Entity Declaration R.H.Khade 4 7/2/2015

5 Entity Declaration For Half Adder R.H.Khade 5 7/2/2015

6 Entity Entity Declaration: Indicates what comes in and what goes out. entity name port namesport mode (direction) port type punctuation 7/2/2015 6 R.H.Khade

7 The port type for this entity have been specified to be of type BIT, which means that the ports can take the values ‘0’ or ‘1’. R.H.Khade 7 7/2/2015

8 Entity declaration for the 2-to-4 decoder circuit. R.H.Khade 8 7/2/2015

9 BIT_VECTOR is a predefined unconstrained array type of BIT. entity DECODER2×4 is Port (A, B, ENABLE: in BIT; Z:out BIT_VECTOR(0 to 3)); end DECODER2×4; R.H.Khade 9 7/2/2015

10 The range ”0 to 3” for port Z specifies the array size. An unconstrained array type is a type in which the size of the array is not specified. R.H.Khade 10 7/2/2015

11 Architecture – All entities that can be simulated have an architecture description. The architecture describes the behavior of the entity.. Each VHDL design unit comprises an "entity" declaration and one or more "architectures". 7/2/2015 11 R.H.Khade

12 12 7/2/2015 Architecture Body The internal details of an entity are specified by an architectural body using any of the following modeling style:

13 4) As any combination of previous three. 3) As a set of sequential assignments (to represent behavior) R.H.Khade 13 7/2/2015 1)As a set of interconnected components (to represent structure) 2) As a set of concurrent assignment statements (to represent dataflow)

14 Dataflow model of HALF_ADDER described usig two concurrent signal assignment statements. R.H.Khade 14 7/2/2015

15 Architecture of full adder entity name port namesport mode (direction) port type reserved words punctuation 7/2/2015 15 R.H.Khade

16 1) Structural style of modeling. 2) Dataflow style of modeling 3) Behavioral style of modeling Architecture Modeling Style R.H.Khade 16 7/2/2015

17 In the structural style of modeling, an entity is described as a set of interconnected components R.H.Khade 17 7/2/2015

18 In the structural style of modeling, the architecture body is composed of two parts: 1) The declarative part before the keyword begin. 2) The statement part after the keyword begin. R.H.Khade 18 7/2/2015

19 The declared components are instantiated in the statement part of the architecture body using component instantiation statements. X1 and A1 are the component labels for these component instantiation R.H.Khade 19 7/2/2015

20 The first component instantiation statement labeled X1, shows that signals A and B (the input ports of the HALF_ADDER) are connected to the X and Y input ports of a XOR2 component, while output port Z of this component is connected to output port SUM R.H.Khade 20 7/2/2015

21 Separate entity models should be written for the components XOR2 and AND2. The signals in the port map of a component instantiation and the port signals in the component declaration are associated by position called positional association. R.H.Khade 21 7/2/2015

22 A component instantiation statement is a concurrent statement. The order of these statements is not important. R.H.Khade 22 7/2/2015

23 The structural style of modeling describes only an interconnection of components (viewed as black boxes), without implying any behavior of the components. R.H.Khade 23 7/2/2015

24 Architecture of the DECODER2×4 using structural representation R.H.Khade 24 7/2/2015

25 BIT_VECTOR is a predefined unconstrained array type of BIT. entity DECODER2×4 is Port (A, B, ENABLE: in BIT; Z:out BIT_VECTOR(0 to 3)); end DECODER2×4; R.H.Khade 25 7/2/2015

26 R.H.Khade 26 7/2/2015

27 The architecture body contains a signal declaration that declares two signals, ABAR and BBAR, of type BIT. These signals, which represent wires, are used to connect components. The scope of these signals is restricted to the architecture body; and therefore these signals are not visible outside the architecture body. R.H.Khade 27 7/2/2015

28 Architecture Defines one particular implementation of a design unit architecture arch_name of entity_name is... declarations... // can be data types, constants, signals, etc begin... concurrent statements … end Concurrent statements describe a design unit at one or more levels of modeling abstraction:  Behavioral Model: No structure implied. Usually written in sequential, procedural style.  Dataflow Model: All datapaths shown, plus all control signals.  Structural Model: Interconnection of components. 7/2/2015 28 R.H.Khade

29 29 7/2/2015

30 Let’s Start Simple Support different description levels  Structural (specifying interconnections of the gates),  Dataflow (specifying logic equations), and  Behavioral (specifying behavior) 7/2/2015 30 R.H.Khade

31 Arithmetic and Logical Expressions Expressions in VHDL are similar to those of most high-level languages. Data elements must be of the type, or subtypes of the same base type. Operators include the following: Logical: and, or, nand, nor, xor, not (for boolean or bit ops) Relational: =, /=,, >= Arithmetic: +, -, *, /, mod, rem, **, abs (a mod b takes sign of b, a rem b takes sign of a) Concatenate: & (ex. a & b makes one array) Examples a <= b nand c; d := g1 * g2 / 3; Bus_16 <= Bus1_8 & Bus2_8; 7/2/2015 31 R.H.Khade

32 VHDL Data Types Each VHDL object must be classified as being of a specific data type. Predefined Scalar Data Types (single objects)  bit values: '0', '1', boolean values: TRUE, FALSE  integer values: -(231) to +(231 - 1)  natural values: 0 to integer'high (subtype of integer)  character values: ASCII characters (eg. 'A')  time values include units (eg. 10ns, 20us) Predefined VHDL Aggregate Data Types  bit_vector array (natural range <>) of bit Example : signal dbus: bit_vector(15 downto 0); Accessing element: dbus(n) example: dbus(0)  string array (natural range <>) of char 7/2/2015 32 R.H.Khade

33 VHDL Objects: Variables A variable is declared within a block, process, procedure, or function, and is updated immediately when an assignment statement is executed. Can be of any scalar or aggregate data type, Is utilized primarily in behavioral descriptions. Declaration syntax: variable symbol: type [:= initial_value]; Example: process variable count: integer := 0; variable rega: bit_vector(7 downto 0); begin... count := 7; -- assign values to variables rega := x"01"; end; 7/2/2015 33 R.H.Khade

34 VHDL Objects: Signals A signal is an object with a history of values (related to "event" times, i.e. times at which the signal value changes). Signals are declared via signal declaration statements or entity port definitions, and may be of any data type. Declaration syntax : signal sig_name: data_type [:=initial_value]; Example: signal clock: bit; Signal assignment statement: A <= B after 10ns; 7/2/2015 34 R.H.Khade

35 Modeling Flip-Flops Using VHDL Processes Whenever one of the signals in the sensitivity list changes, the sequential statements are executed in sequence one time General form of process 7/2/2015 35 R.H.Khade

36 D Flip-flop Model Bit values are enclosed in single quotes 7/2/2015 36 R.H.Khade

37 JK Flip-Flop Model 7/2/2015 37 R.H.Khade

38 JK Flip-Flop Model 7/2/2015 38 R.H.Khade

39 Backup 7/2/2015 39 R.H.Khade

40 Object Attributes An object attribute returns information about a signal or data type. Signal Condition Attributes (for a signal S) S'DELAYED(T) - value of S delayed by T time units S'STABLE(T) - true if no event on S over last T time units S'QUIET(T) - true if S quiet for T time units S'LAST_VALUE - value of S prior to latest change S'LAST_EVENT - time at which S last changed S'LAST_ACTIVE - time at which S last active S'EVENT - true if an event has occurred on S in current cycle S'ACTIVE - true if signal S is active in the current cycle S'TRANSACTION - bit value which toggles each time signal S changes 7/2/2015 40 R.H.Khade

41 Constants A constant associates a value to a symbol of a given data type Declaration syntax: constant symbol: type := value; Example: constant zero4: bit_vector(0 to 3) := ('0','0','0','0'); 7/2/2015 41 R.H.Khade

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