1. ELEN 468 Lecture 251 ELEN 468 Advanced Logic Design Lecture 25 Built-in Self Test

2. ELEN 468 Lecture 252 BIST ( Built-in Self Test ) PRPG: Pseudo Random Pattern Generator ORA: Output Response Analyzer CUT: Circuit Under Test PRPG CUT ORA Start Pass/fail PIPO

3. ELEN 468 Lecture 253 BIST Motivation Useful for field test and diagnosis (less expensive than a local automatic test equipment)

4. ELEN 468 Lecture 254 Design and test + / - Fabri- cation + Manuf. Test - Level Chips Boards System Maintenance test - Diagnosis and repair - Service interruption - + Cost increase - Cost saving +/- Cost increase may balance cost reduction Benefits and Costs of BIST

5. ELEN 468 Lecture 255 Economics – BIST Costs  Chip area overhead for: Test controller Hardware pattern generator Hardware response compacter Testing of BIST hardware  Pin overhead – at least 1 pin needed to activate BIST operation  Performance overhead – extra path delays  Reliability reduction – due to increased area and complexity

6. ELEN 468 Lecture 256 BIST Benefits  Reduced testing and maintenance cost  Lower test generation cost  Reduced storage / maintenance of test patterns  Simpler and less expensive ATE  Can test many units in parallel  Shorter test application times  Can test at functional system speed

7. ELEN 468 Lecture 257 BIST Types On-line BIST Concurrent Non-concurrent Off-line BIST Functional Structural

8. ELEN 468 Lecture 258 BIST Architecture

9. ELEN 468 Lecture 259 Pseudo-Random Pattern Generation through LFSR Linear Feedback Shift Register (LFSR)  Produces patterns algorithmically – repeatable  Has most of desirable random # properties Long sequences needed for good fault coverage

10. ELEN 468 Lecture 2510 Response Compaction Severe amounts of data in CUT response to LFSR patterns – example:  Generate 5 million random patterns  CUT has 200 outputs  5 million x 200 = 1 billion bits response Uneconomical to store and check all of these responses on chip Responses must be compacted

11. ELEN 468 Lecture 2511 LFSR for Response Compacter

12. ELEN 468 Lecture 2512 Signature Analysis Signature – any statistical circuit property distinguishing between bad and good circuits Aliasing – due to information loss, signatures of good and some bad machines match Signature analysis – compare good machine response into good machine signature. Actual signature generated during testing, and compared with good machine signature

13. ELEN 468 Lecture 2513 BILBO (Built-in Logic Block Observer) Four modes: 1. Flip-flop 2. LFSR pattern generator 3. LFSR response compacter 4. Scan chain for flip-flops

14. ELEN 468 Lecture 2514 Example of BILBO Combined functionality of D flip-flop, pattern generator, response compacter and scan chain

15. ELEN 468 Lecture 2515 BILBO Serial Scan Mode B1 B2 = “00” Dark lines show enabled data paths

16. ELEN 468 Lecture 2516 BILBO LFSR Pattern Generator Mode B1 B2 = “01”

17. ELEN 468 Lecture 2517 BILBO in D-FF (Normal) Mode B1 B2 = “10”

18. ELEN 468 Lecture 2518 BILBO in Response Compactor Mode B1 B2 = “11”

19. ELEN 468 Lecture 2519 Exercises 7

20. ELEN 468 Lecture 2520 Problem 1 always @ ( … ) begin for ( j = 0; j < n; j = j + 1 ) begin a[j] = 0; for ( k = 0; k < j; k = k + 1 ) @ ( posedge clock ) a[j] = a[j] + x[k]; end always @ ( … ) begin for ( j = 0; j < n; j = j + 1 ) begin a[j] = 0; for ( k = 0; k < j; k = k + 1 ) @ ( posedge clock ) a[j] = a[j] + x[k]; end always @ ( … ) begin … a[0] = 0; for ( j = 0; j < n; j = j + 1 ) begin @ ( posedge clock ) a[j] = a[j-1] + x[j-1]; end always @ ( … ) begin … a[0] = 0; for ( j = 0; j < n; j = j + 1 ) begin @ ( posedge clock ) a[j] = a[j-1] + x[j-1]; end

21. ELEN 468 Lecture 2521 Problem 2 Flip-flop a y x b cz Latch clock

22. ELEN 468 Lecture 2522 Problem 3.1 + Reg a Reg b Reg c + +

23. ELEN 468 Lecture 2523 Problem 3.2 + Reg a Reg b Reg c + +