1. ©2010 Cengage Learning Engineering. All Rights Reserved.10-0 Introduction to VHDL PowerPoint Presentation © 2010. Cengage Learning, Engineering. All Rights Reserved. 1-0 UNIT 10

2. ©2010 Cengage Learning Engineering. All Rights Reserved.10-1 Figure 10.1 Gate Circuit

3. ©2010 Cengage Learning Engineering. All Rights Reserved.10-2 Figure 10.2 Inverter with Feedback

4. ©2010 Cengage Learning Engineering. All Rights Reserved.10-3 Figure 10.3 Three Gates with a Common Input and Different Delays

5. ©2010 Cengage Learning Engineering. All Rights Reserved.10-4 Figure 10.4 Array of AND Gates

6. ©2010 Cengage Learning Engineering. All Rights Reserved.10-5 Figure 10.5 2-to-1 Multiplexer

7. ©2010 Cengage Learning Engineering. All Rights Reserved.10-6 Figure 10.6 Cascaded 2-to-1 MUXes

8. ©2010 Cengage Learning Engineering. All Rights Reserved.10-7 Figure 10.7 4-to-1 Multiplexer

9. ©2010 Cengage Learning Engineering. All Rights Reserved.10-8 Figure 10.8 VHDL Module with Two Gates

10. ©2010 Cengage Learning Engineering. All Rights Reserved.10-9 Figure 10.9 VHDL Program Structure

11. ©2010 Cengage Learning Engineering. All Rights Reserved.10-10 Figure 10.10 Entity Declaration for a Full Adder Module

12. ©2010 Cengage Learning Engineering. All Rights Reserved.10-11 Figure 10.11 4-Bit Binary Adder

13. ©2010 Cengage Learning Engineering. All Rights Reserved.10-12 Figure 10.12 Structural Description of 4-Bit Adder

14. ©2010 Cengage Learning Engineering. All Rights Reserved.10-13 Figure 10.13 VHDL Description of a ROM

15. ©2010 Cengage Learning Engineering. All Rights Reserved.10-14 Figure 10.14 Comparator for Integers

16. ©2010 Cengage Learning Engineering. All Rights Reserved.10-15 Figure 10.15 NOR-NOR Circuit and Structural VHDL Code

17. ©2010 Cengage Learning Engineering. All Rights Reserved.10-16 Figure 10.16 Tri-State Buffer

18. ©2010 Cengage Learning Engineering. All Rights Reserved.10-17 Figure 10.17 Tri-State Buffer Driving a Bus

19. ©2010 Cengage Learning Engineering. All Rights Reserved.10-18 Figure 10.18 Resolution Function for Two Signals

20. ©2010 Cengage Learning Engineering. All Rights Reserved.10-19 Figure 10.19 VHDL Code for Binary Adder

21. ©2010 Cengage Learning Engineering. All Rights Reserved.10-20 Figure 10.20 VHDL Code for Bi- Directional I/O Pin

22. ©2010 Cengage Learning Engineering. All Rights Reserved.10-21 Figure 10.21 Compilation, Simulation, and Synthesis of VHDL Code

23. ©2010 Cengage Learning Engineering. All Rights Reserved.10-22 Figure 10.22 Simulation of VHDL Code

24. ©2010 Cengage Learning Engineering. All Rights Reserved.10-23 Images From End of Chapter Problems Problem 10.1

25. ©2010 Cengage Learning Engineering. All Rights Reserved.10-24 Problem 10.11

26. ©2010 Cengage Learning Engineering. All Rights Reserved.10-25 Problem 10.16

27. ©2010 Cengage Learning Engineering. All Rights Reserved.10-26 Problem 10.17

28. ©2010 Cengage Learning Engineering. All Rights Reserved.10-27 Problem 10.18

29. ©2010 Cengage Learning Engineering. All Rights Reserved.10-28 Problem 10.19

30. ©2010 Cengage Learning Engineering. All Rights Reserved.10-29 Problem 10.20

31. ©2010 Cengage Learning Engineering. All Rights Reserved.10-30 Problem 10.21

32. ©2010 Cengage Learning Engineering. All Rights Reserved.10-31 Problem 10.H