1. Lecture 14: Wires

2. Outline Introduction Interconnect Modeling Wire Resistance
Wire Capacitance
Wire RC Delay
Crosstalk
Wire Engineering
Repeaters
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3. Introduction Chips are mostly made of wires called interconnect
In stick diagram, wires set size
Transistors are little things under the wires
Many layers of wires
Wires are as important as transistors
Speed
Power
Noise
Alternating layers run orthogonally
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4. Wire Geometry Pitch = w + s Aspect ratio: AR = t/w
Old processes had AR << 1
Modern processes have AR  2
Pack in many skinny wires
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5. Layer Stack AMI 0.6 mm process has 3 metal layers
M1 for within-cell routing
M2 for vertical routing between cells
M3 for horizontal routing between cells
Modern processes use metal layers
M1: thin, narrow (< 3l)
High density cells
Mid layers
Thicker and wider, (density vs. speed)
Top layers: thickest
For VDD, GND, clk
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6. Example Intel 90 nm Stack Intel 45 nm Stack 14: Wires [Thompson02]
[Moon08]
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7. Intel 45nm Stack Layer t (nm) w (nm) s (nm) Pitch (nm) M9 7000 17500
13000
30500 M8
720
400
410
810 M7
504
280
560 M6
324
180
360 M5
252
140 M4
216
120
240 M3
144 80
100
160 M2 M1
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8. Intel 45nm Stack
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9. Interconnect Modeling
Current in a wire is analogous to current in a pipe
Resistance: narrow size impedes flow
Capacitance: trough under the leaky pipe must fill first
Inductance: paddle wheel inertia opposes changes in flow rate
Negligible for most
wires
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10. Impact of Interconnect
Reduce reliability
Affect performance
Increase tp
Increase energy dissipation
Cause the introduction of extra noise sources
Inductive effects usually ignored
Resistive effects ignored if wire is short
Interwire capacitance usually ignored if overlap is small
Wire capacitance is dominant
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11. Wire Models
Capacitance-only
All-inclusive model

12. Capacitance of Wire Interconnect

13. Capacitance: The Parallel Plate Model

14. Permittivity

15. Fringing Capacitance

16. Fringing Capacitance
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17. Fringing Capacitance Some other formulas
This empirical formula is accurate to 6% for AR < 3.3
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18. Fringing versus Parallel Plate

19. Wire Capacitance Wire has capacitance per unit length To neighbors
To layers above and below
Ctotal = Ctop + Cbot + 2Cadj
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20. Interwire Capacitance

21. Capacitance Trends Parallel plate equation: C = eoxA/d
Wires are not parallel plates, but obey trends
Increasing area (W, t) increases capacitance
Increasing distance (s, h) decreases capacitance
Dielectric constant
eox = ke0
e0 = 8.85 x F/cm
k = 3.9 for SiO2
Processes are starting to use low-k dielectrics
k  3 (or less) as dielectrics use air pockets
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22. M2 Capacitance Data Typical dense wires have ~ 0.2 fF/mm
Compare to 1-2 fF/mm for gate capacitance
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23. Impact of Interwire Capacitance

24. Capacitance of Dense Wires
An empirical equation is
Also, floating capacitors occur, which
Create noise
Affect performance
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25. Wiring Capacitances
We typically use simple models for capacitance, given by
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26. Wiring Capacitances (0.25 mm CMOS)

27. Diffusion & Polysilicon
Diffusion capacitance is very high (1-2 fF/mm)
Comparable to gate capacitance
Diffusion also has high resistance
Avoid using diffusion runners for wires!
Polysilicon has lower C but high R
Use for transistor gates
Occasionally for very short wires between gates
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28. Wire Resistance r = resistivity (W*m) R = sheet resistance (W/)
 is a dimensionless unit(!)
Count number of squares
R = R * (# of squares)
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29. Sheet Resistance

30. Choice of Metals Until 180 nm generation, most wires were aluminum
Contemporary processes normally use copper
Cu atoms diffuse into silicon and damage FETs
Must be surrounded by a diffusion barrier
Metal
Bulk resistivity (mW • cm)
Silver (Ag)
1.6
Copper (Cu)
1.7
Gold (Au)
2.2
Aluminum (Al)
2.8
Tungsten (W)
5.3
Titanium (Ti)
43.0
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31. Contacts Resistance Contacts and vias also have 2-20 W
Use many contacts for lower R
Many small contacts for current crowding around periphery
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32. Copper Issues Copper wires diffusion barrier has high resistance
Copper is also prone to dishing during polishing
Effective resistance is higher
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33. Example
Compute the sheet resistance of a 0.22 mm thick Cu wire in a 65 nm process. Ignore dishing.
Find the total resistance if the wire is mm wide and 1 mm long. Ignore the barrier layer.
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34. Skin Effect
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35. Skin Effect
Define a skin depth, d, where the current falls to 1/e of its nominal value.
Here, m is the permeability of the surrounding dielectric and has a typical value of approximately 4p X 10-7 for all dielectrics.
For Al at 1 GHz, d = 2.6mm.
To see the effect, assume a rectangular wire.
Assume that the current flows only in the skin as defined above
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36. Skin Effect
The cross section is given by H W
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37. Skin Effect Using this cross sectional area,
We can define a frequency fs where the skin depth is half the highest dimension of the conductor.
It is not meaningful to increase the dimensions beyond that point for that frequency.
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38. Skin Effect
For Al in SiO2, at 1GHz fs, the largest dimension should be 5.2mm.
Actual results show 30% increase in R due to skin effect for a 20mm wire and 2% for a 1mm wire.
One other thing to note is that the actual frequency of the square wave should not be used.
A sine wave whose rise and fall times equal to the rise and fall times of the square wave will give more accurate results.
For 20% - 80% rise and fall, the equivalent
frequency is given by
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39. Skin Effect
As another example, choose copper in SiO2 with 20ps edge rates.
f=5.8GHz, d = 0.99mm
Note that the resistivity of metals drops at very low temperatures.
For example, an order of magnitude improvement at 77K (liquid nitrogen).
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40. Inductance We will ignore inductance in this course
Inductance causes voltage variations
Inductance causes extra impedance.
Remember where
c: capacitance per unit length
l: inductance per unit length
e: permittivity of the surrounding dielectric
m: permeability of the surrounding dielectric
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41. Inductance Also, remember that Dielectric er Prop. Speed (cm/ns)
Vacuum 1 30
SiO2
3.9 15
PC Board (epoxy glass)
5.0 13
Alumina (ceramic packages)
9.5 10
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42. Inductance How do we use this information? From a previous table,
c (aF/mm)
l (pH/mm)
W = 0.4mm 92
0.47
W = 1mm
110
0.39
W = 10mm
380
0.11
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43. Inductance Using Equating the impedances, Z = wl
For a 1mm wide wire, r = Z at 30GHz.
Inductance is not an issue for now.
Typically, lower level metals are microstrips whose inductances are given by
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44. Inductance
On-chip inductance is important for wires where the speed of light flight time is longer than either the rise times of the circuits or the RC delay of the wire.
This can be expressed as
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45. Inductance
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46. Inductance
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47. Lumped Element Models Wires are a distributed system
Approximate with lumped element models
3-segment p-model is accurate to 3% in simulation
L-model needs 100 segments for same accuracy!
Use single segment p-model for Elmore delay
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48. The Lumped Model

49. Wire RC Delay
Estimate the delay of a 10x inverter driving a 2x inverter at the end of the 1 mm wire. Assume wire capacitance is 0.2 fF/mm and that a unit-sized inverter has R = 10 KW and C = 0.1 fF.
tpd = (1000 W)(100 fF) + ( W)( fF) = 281 ps
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50. Wire Energy
Estimate the energy per unit length to send a bit of information (one rising and one falling transition) in a CMOS process.
E = (0.2 pF/mm)(1.0 V)2 = 0.2 pJ/bit/mm
= 0.2 mW/Gbps
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51. Elmore Delay
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52. Elmore Delay
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53. The Elmore Delay - RC Chain

54. Wire Model Assume: Wire modeled by N equal-length segments
For large values of N:

55. The Distributed RC Line
For a distributed line, we have the diffusion equation
This equation has a solution in the s domain
Vout(t) cannot be solved in closed form.
It can be approximated by
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56. Step-response as a function of time and space

57. RC Wires – Lumped vs Distributed
Value of Interest
Lumped RC
Distributed RC
0 -> 50% (tp)
0.69RC
0.38RC
0 -> 63% (t) RC
0.5RC
10% -> 90% (tr)
2.2RC
0.9RC
0 -> 10%
0.1RC
0 -> 90%
2.3RC
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58. Distributed RC Lines
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59. Distributed RC Lines
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60. The Transmission Line
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61. The Transmission Line The diffusion equations are
First, ignore r. This is a lossless transmission line.
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62. The Transmission Line
A step input applied to a lossless transmission line propagates through the line with speed v.
Z0 is the characteristic impedance and is independent of length.
Z0 is between 100W and 500W for typical wires.
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63. The Transmission Line Define a wave reflection coefficient as
When a transmission line is being driven by an ideal source, the termination is important.
For a termination of Z0, no reflection.
For a short circuit termination, r = -1
For an open circuit termination, r = 1
See the site
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64. The Transmission Line
Case 1: Large source resistance and infinite load resistance. Take RS = 5Z0
Cycle 1:
When this wave reaches the destination, it is fully reflected -> 1.67V.
It comes back to the source. The source has become the load.
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65. The Transmission Line Case 1 continued The new source voltage becomes
We restart the analysis with 1.1 V for cycle 2.
It is obvious that the signal builds up.
However, the rise time is not determined by any RC constant. It is in terms of number of reflection cycles given by length/velocity.
See the site
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66. The Transmission Line
Case 2: Small source resistance, infinite load resistance.
Almost all the signal injected into the transmission line.
Reflected from the load. Almost doubles by the time it comes back to the source.
The signal is phase reversed at the source as
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67. The Transmission Line Case 2: The signal exhibits severe ringing.
It takes many cycles before it settles to its final value.
Case 3: Matched source resistance.
Half the signal is injected into the line
Doubles at the termination.
Final value is reached within length/velocity.
Capacitive termination (our case)
No overshoot, behavior asymptotic to t = Z0CL
Interesting behavior observed only at source.
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68. A Look into the Future Ideal Scaling
Typically, S = 1.15, SC = 0.94 per year.
Delay of global wires increases 50% per year.
Parameter
Relation
Local Wire
Constant Length
Global Wire
W, H, t
1/S L 1
1/SC C
LW/t R
L/WH S S2
S2/SC RC
L2/Ht
S2/S2C
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69. A Look into the Future Constant R scaling
eC is introduced to model the extra fringing capacitance effects.
As long as eC < S, not too bad.
Parameter
Relation
Local Wire
Constant Length
Global Wire
W,t
1/S H 1 L
1/SC C
eCLW/t
eC/S eC
eC/SC R
LW/H S
S/SC RC
eCL2/Ht
eCS
eCS/S2C
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70. Crosstalk
A capacitor does not like to change its voltage instantaneously.
A wire has high capacitance to its neighbor.
When the neighbor switches from 1-> 0 or 0->1, the wire tends to switch too.
Called capacitive coupling or crosstalk.
Crosstalk effects
Noise on nonswitching wires
Increased delay on switching wires
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71. Crosstalk Delay Assume layers above and below on average are quiet
Second terminal of capacitor can be ignored
Model as Cgnd = Ctop + Cbot
Effective Cadj depends on behavior of neighbors
Miller effect B DV
Ceff(A)
MCF
Constant
VDD
Cgnd + Cadj 1
Switching with A
Cgnd
Switching opposite A
2VDD
Cgnd + 2 Cadj 2
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72. Crosstalk Noise Crosstalk causes noise on nonswitching wires
If victim is floating:
model as capacitive voltage divider
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73. Driven Victims Usually victim is driven by a gate that fights noise
Noise depends on relative resistances
Victim driver is in linear region, agg. in saturation
If sizes are same, Raggressor = 2-4 x Rvictim
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74. Coupling Waveforms
Simulated coupling for Cadj = Cvictim
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75. Noise Implications So what if we have noise?
If the noise is less than the noise margin, nothing happens
Static CMOS logic will eventually settle to correct output even if disturbed by large noise spikes
But glitches cause extra delay
Also cause extra power from false transitions
Dynamic logic never recovers from glitches
Memories and other sensitive circuits also can produce the wrong answer
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76. Wire Engineering
Goal: achieve delay, area, power goals with acceptable noise
Degrees of freedom:
Width
Spacing
Layer
Shielding
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77. Repeaters R and C are proportional to l RC delay is proportional to l2
Unacceptably great for long wires
Break long wires into N shorter segments
Drive each one with an inverter or buffer
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78. Repeater Design How many repeaters should we use?
How large should each one be?
Equivalent Circuit (Using the PI model)
Wire length l/N
Wire Capacitance Cw*l/N, Resistance Rw*l/N
Inverter width W (nMOS = W, pMOS = 2W)
Gate Capacitance C’*W, Resistance R/W
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79. Repeater Results Write equation for Elmore Delay
Differentiate with respect to W and N
Set equal to 0, solve
~40 ps/mm
in 65 nm process
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80. Repeater Energy Energy / length ≈ 1.87CwVDD2
87% premium over unrepeated wires
The extra power is consumed in the large repeaters
If the repeaters are downsized for minimum EDP:
Energy premium is only 30%
Delay increases by 14% from min delay
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81. Repeaters
Let us detail the derivation. It is simpler if distributed analysis is used.
Using Elmore formulation,
If there are k identical inverters,
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82. Repeaters Make some approximations to make problem simpler.
Ignore Cint and collect terms
Take the derivative to find the optimum
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83. Repeaters Now, let us try to size the repeaters as well.
Let us use h to scale them.
Now, taking two partial derivatives,
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