1. Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs W. H. Liu, M. S. Chang and T. C. Wang Department of Computer Science, NTHU, Taiwan DAC 2014

2. Outline Introduction Preliminaries Enumeration-based Floorplanning Algorithm Network-flow-based Signal Assignment Experimental Results Conclusions

3. Introduction Interposer-based 3D ICs (2.5D ICs) have been seen as an alternative approach to true 3D stacked ICs. 2.5D ICs use a silicon interposer as an interface between a package and dies, and mount each die on the interposer. 2.5D ICs are easier to fabricate than true 3D ICs, making 2.5D ICs become more popular.

4. Introduction

5. This paper assumes that the placement and routing in each die are already finished. The locations of the I/O buffers in each die are determined. The work focuses on optimizing the multi-die floorplanning and signal assignment in a 2.5D IC to minimize the total wirelength.

6. Preliminaries Wirelength Evaluation  The interconnects to deliver signals in 2.5D ICs are classified into three types of nets: Intra-die nets Internal nets External nets  The total wirelength (TWL) is measured by:

7. Problem Formulation Multi-die Floorplanning Problem:  Given: D: a set of dies in a 2.5D IC S: a set of signals B: a set of I/O buffers in each die E: a set of escaping points at the boundaries of the package on the PCB A fixed outline silicon interposer  Output: Find a floorplan F of all dies in D on the interposer Die-to-die and die-to-boundary spacing constraints are imposed and need to be satisfied

8. Problem Formulation Signal Assignment Problem  Given F: a floorplan S: a set of signals B: a set of I/O buffers in each die M: a set of micro-bumps in each die E: a set of escaping points at the boundaries of the package on the PCB T: a set of TSVs in the interposer  Output Assign the signal of each I/O buffer in B to a micro-bump in M Assign the signal of each escaping point in E to a TSV in T such that no micro-bump or TSV is assigned more than one signal

9. Problem Formulation Multi-die floorplanning resultSignal assignment result

10. Enumeration-based Floorplanning Algorithm Estimate TWL by adding up the HPWL of all terminals for every signal. Violate the fixed outline constraint or the spacing constraints

11. Enumeration-based Floorplanning Algorithm Illegal Branch Cutting  Each sequence pair with different die orientations provides at most 4 n different floorplans.  If a SP does not provide any legal floorplans, we can avoid exploring the floorplans of this SP.  F low : rotate each die to make its height not greater than its width.  F thin : rotate each die to make its width not greater than its height.  If F low is taller than the interposer or F thin is wider than the interposer, SP has no legal floorplan.

12. Enumeration-based Floorplanning Algorithm Inferior Branch Cutting  If we can predict that all floorplans of a SP are worse than the current F best, we can avoid exploring the floorplans of the SP.  Let L min denote a lower bound on WL with respect to a SP.  If L min is longer than the WL of F best, we can claim that all floorplans of SP are worse than F best. The exploration of the floorplans of SP can be skipped.

13. Enumeration-based Floorplanning Algorithm Inferior Branch Cutting  Let L min consist of LX min and LY min.  Estimate LY min by adding up the minimum vertical WL of each signal in F low.

14. Enumeration-based Floorplanning Algorithm Die Orientation Pre-determination  Generate a reference floorplan F ref before EFA.  EFA only explores the floorplans whose die orientations are the same as F ref.  Two-stage greedy packing algorithm Choose a best pair of dies and packs them together to form the initial F ref. Iteratively attach one of unpacked dies to until all dies are packed into F ref.

15. Enumeration-based Floorplanning Algorithm Puts F pair to the center of interposer, calaulate the total HPWL of all signals in F pair If F pair is illegal, a very large penalty is added to the cost of F pair

16. Enumeration-based Floorplanning Algorithm

17. Network-flow-based Signal Assignment Divide the SAP into several sub problems. First solve the sub-SAP for micro-bumps die-by-die. Solve the sub-SAP for TSVs. Solve the sub-SAP for each die in a decreasing order based on the number of I/O buffers in each die.

18. Network-flow-based Signal Assignment

20. Window Matching Method to Accelerate  Use a window matching method to identify the assignment candidates for each I/O buffer.  For each I/O buffer b i,x, create a window w i,x whose center is b i,x, and its width and height are 2xm pitch, where m pitch denotes the pitch between micro-bumps.  If M(w i,x )-B(w i,x )<, iteratively extend each boundary of w i,x by m pitch until M(w i,x )-B(w i,x )≥.  Only build the edges from each I/O buffer b i,x to the micro- bumps in w i,x.

21. Experimental Results

25. Conclusions This paper addresses a multi-die floorplanning problem and a signal assignment problem to shorten the interconnects in 2.5D ICs. An enumeration-based floorplanning algorithm is presented with three acceleration techniques.