1. Pei-Ci Wu Martin D. F. Wong On Timing Closure: Buffer Insertion for Hold-Violation Removal DAC’14

2. Outline Introduction Preliminaries Linear Programming Based Optimization Bottom-up Buffer Insertion Experimental Results Concluding Remarks

3. Introduction Timing closure, which is to satisfy the timing constraints, is a key problem in the physical design Setup (long-path) constraints  ensure that the signal transitions do not arrive too late hold-time (short-path) constraints  ensure that the signal transitions do not arrive too early

4. Typically, hold violations are addressed after setup optimization has been performed. Discrete cell sizes (i.e. discrete buffer sizes for hold optimization) in modern industrial designs

5. Cell libraries specified for the setup constraints and the hold-time constraints are usually different in modern industrial designs

6. Preliminaries Negative setup slacks and negative hold slacks indicate setup violations and hold violations

7. TNS  the absolute value of the total negative setup slacks of all the pins in PO THS  the absolute value of the total negative hold slacks of all the pins in PO TNS must not be worsen during hold- violation removal

8. Given:  a design and a buffer library, find a buffering solution such that:  THS and the cost of buffering (i.e. area and power consumption) are both minimized while TNS is not worsen.

9. Linear Programming Based Optimization Inserting delay into wires to remove hold violations  A linear programming formulation  Extend such formulation for the complex timing constraints  Graph-reduction approach

10. Input  Combinational circuit C* s.t. for any pin p of C*, hold_slack p 0 C* can then be represented as a directed acyclic graph G(V,E)  V is the pins of C*  ( i, j ) ∈ E represents an edge

11. I : the zero in-degree pins O : the zero out-degree pins for each pin i in V  three real-value variables, x i (delays inserted at pin i for hold-time constraints), ha i, and sa i

12. Hold-time constraints

13. For buffer library characterization is necessary in order to get an empirical ratio such that we assume that the buffer only affects the driver cell and the sink cells of the buffer

14. Delays introduced by inserting the buffer is  (a)  (b)

15. Setup constraints

16. Objective : The setup constraints limit the delays that can be inserted r i is only necessary when there is no feasible solution

17. Some pins with positive setup slacks and positive hold slacks that are not included

18. Complex Timing Constraints  multiple clock domains  multiple cycles  different clock phases within one clock domain

19. Graph Reduction

20. Bottom-up Buffer Insertion Given:  a pin i, hold delay D H and setup delay D S Find a buffering solution at pin i from a buffer library B:  hold delays introduced by the chosen buffers are as close to D H  setup delays introduced by the chosen buffers are not larger than D S  Minimize the area of the chosen buffers

21. DP based algorithm A set of buffering candidates C(L, d h, d s, A) is kept during the process For each buffer in B, we insert it to any of the existing candidates

22. New buffering candidates  (1) if d′ s > D S, C′ is removed immediately  (2) if d′ h <= d h, C′ is removed as well d′ h > D H + margin where margin is a parameter, then C′ is removed too  (3) C′ is dominated by any existing candidate C*(I*, d* h, d* s, A*) if d′ h A* Chose the candidate that has the largest ratio of d h /A as the buffering solution

23. Bottom-up Methodology  process the pins by the bottom-up topological ordering (i.e. from PO to PI) DP algorithm cannot realize the exact amount of hold delays/setup delays by inserting buffers(extra delays)

24. Suppose now we are processing pin p, collected extra delays  cur_setup_req p = setup_req p − ds_delay  extra delays = cur_setup_req p – sa p  D s = x p + cur_setup_req p − sa p  Similarly to get D h

25. Optimization Flow

26. Experimental Results

28. Concluding Remarks First propose a linear programming based approach that minimizes the number of inserted delays A bottom-up buffer insertion and the flow of optimizing are presented