1. © Fraunhofer IMS Version 6.1. Image Sensor Design and Technology Development at Fraunhofer IMS Dr. Sascha Weyers

2. © Fraunhofer Fraunhofer IMS Infrastructure – CMOS Fab Total area:1300 m 2 Clean room class: 10 Wafer size: 200 mm (8 inch; 0.35 µm) Staff: working in 4 shifts / 7 days a week Capacity: > 70.000 Wafer p.a. Excellence of the CMOS-Line Complete CMOS process line plus integrated sensors (SOI, imager, pressure, mixed signal) ICs from a few 100 ASICs to few million

3. © Fraunhofer Fraunhofer IMS Infrastructure – Microsystem Lab&Fab Total area: 600 m² Clean room class: 10 Wafer size: 200 mm Mission Extending the application areas of CMOS (“More than Moore”) by post processing on CMOS wafers. Development Activities Adding layers, structures, devices onto preprocessed “intelligent substrates” (CMOS wafers) to create integrated sensor systems. Examples: micro bolometer arrays for IR imaging, biosensors, opto sensors.

4. © Fraunhofer Fraunhofer IMS Infrastructure – CMOS Backend Total area:300 m² Clean room class: 100 - 1000 Wafer size:200 mm Mission Test Wafer & device tests for pilot series Application specific tests Sensor characterisation Assembly Wafer grinding and dicing Die and wire bonding Encapsulation with glob-top or lids solder

5. © Fraunhofer Service and Know-how - Optoelectronic Devices In the field of „Optoelectronic Devices” Fraunhofer IMS is providing: Service and Support Development of novel optoelectronic devices Use of standard CMOS processes: 0.5µm, 0.35µm, and foundry processes Device modeling and optimization with advanced simulation tools Characterization of „test inserts“ to extract and monitor device parameters (capacitance, dark current, spectral response, etc.)

6. © Fraunhofer Service and Know-how - Optical CMOS Sensors In the field of „Optical CMOS Sensors” Fraunhofer IMS is providing: Service and Support Design of customized image sensors and dedicated optical sensors Wafer fabrication in Fraunhofer IMS fab (L035-OPTO) or foundries Electro-optical test on wafer and device level Device qualification Full service from design to fabrication

7. © Fraunhofer Technology - CMOS 0.35µm Process “Opto” The IMS 0.35µm CMOS process “Opto” is providing: Opto Process Features Stitching Planarization UV transparent silicon nitride passivation Salicide-blocking Color filter deposition & microlenses Opto Devices Pinned photodiodes (low noise, low dark current) High temperature photodiodes Dot array photodiodes Lateral Drift-Field Photodetectors (LDPD) Single-Photon Avalanche Diodes (SPADs) Embedded Charge Coupled Devices (CCD)

8. © Fraunhofer 8 LDPD-Pixel Development Starting Point for Lateral Drift-field Photo Diode Key Features CMOS Technology Low Noise / High Sensitivity (high SNR) Non Destructive Readout Time-Dependent Charge Separation Random Reset Multiple Shutter Multiple Window Integration Correlated Double Sampling Feature

9. © Fraunhofer 9 LDPD-Pixel Development Process Simulation for Doping Level Gradient 0200 X (µm) Pixel 1Pixel 2 Implantation Dose 1 Implantation Dose 2

10. © Fraunhofer 10 LDPD-Pixel Development Device Simulation

11. © Fraunhofer Key Elements of the LDPD ToF-Pixel LDPD-Pixel as basic element Charge Collection (CG)-Electrode: MOS-capacitor with gate oxide 4 Transfer Gates (TX1…4): MOS-capacitor with oxide-nitride- oxide (ONO) isolation stack 4 Floating Diffusions (FD1…3,DD): n+-diffusion areas LDPD-Pixel Application Time-of-Flight Pixel

12. © Fraunhofer LDPD-Pixel Application Sensor Architecture Key Elements of the LDPD ToF-Sensor  Pixel Matrix with in-pixel accumulation functionality => reduction of readout noise  TX Level-Shifter and driver high speed driver for high speed charge transfer in the pixels (ns)  CDS stages background light subtraction and/or accumulation => reduction of readout noise

13. © Fraunhofer CDS stages 128x96 pixel matrix pixel driver LDPD-Pixel Application Realization Example: Cadence® Layout A 3D image obtained using the ToF camera Chip Photography

14. © Fraunhofer Embedded CCD Technology Option Development Project ECTICIS Embedded CCD Based Time Delay Integration CMOS Image Sensor CMOS/CCD TDI sensor for earth observation and high resolution scanning Eureca / DLR

15. © Fraunhofer Embedded CCD Charge Transport Cross Section of Test Structure Device Simulation for Test Structure

16. © Fraunhofer Embedded CCD Results: Charge Transport Time [µs] Output [V] Output Output Gain = 0.91 V Charge Transfer Efficiency CTE 128 = 99.95 % (for 128 pixels)

17. © Fraunhofer CMOS-SPAD Development EU Seventh Framework Programme (FP7, 2007-2013) Grant agreement n° 257646.

18. © Fraunhofer CMOS-SPAD Development Integration of SPAD Device in 0.35 µm CMOS Technology Implementation in CMOS technology  Extension of the standard 0.35 µm CMOS technology  Layout for primitive SPAD device Schematic Cross Section of SPAD Device Layout of SPAD Devices for different Diameters

19. © Fraunhofer CMOS-SPAD Development Integration of SPAD Device in 0.35 µm CMOS Technology Process Simulation of SPAD Device (Doping Density) Electrical Device Simulation of SPAD Device (Electrical Field) Characterization of Test Structures for Process Simulation

20. © Fraunhofer CMOS-SPAD Development Characterization of integrated SPAD Device Dark Count Rate for different Excess Voltages Breakdown Voltage for different Diameters

21. © Fraunhofer CMOS-SPAD Development Timing Response FWHM < 100 ps (Ø = 10 µm) FWHM < 140 ps (Ø = 20 - 30 µm) Small wavelength influence (%D FWHM < 5)

22. © Fraunhofer CMOS-SPAD Development Dark Count Rate Cumulative Distribution Function 30 µm SPAD 64 x 32 pixel array 50 µm SPAD 32 x 1 pixel array 100 µm SPAD 32 x 16 pixel array t HOLD = 300 ns < 5% hot SPADs 20 µm SPAD (64 x 32) 2048-pixel array Smart Pixels (pitch = 150 µm) Active quenching circuit Shaping electronic Time to digital converter Counter Memory Buffer 3.14% fill factor for 30 µm SPAD

23. © Fraunhofer CMOS-SPAD Development Back-SPADs 3D Integration

24. © Fraunhofer CMOS-SPAD Development Back-SPAD Process Variants Fully-Depleted (HV) BackSPADsPartially-Depleted (LV) BackSPADs

25. © Fraunhofer CMOS-SPAD Development Back-SPAD Dark Count Rate Comparison with CMOS SPAD Fill Factor BackSPAD > 70% DCR BackSPAD ≈ 40 x DCR CMOS SPAD

26. © Fraunhofer CMOS-SPAD Development Back-SPAD 3D Integration Pads and SPADs on wafer bonded BackSPADs Cross section of SOI wafer after waferbonding and backthinning 4 µm thick Si/SiO2 film

27. © Fraunhofer Image Sensor Design and Technology Development at Fraunhofer IMS Thank you for your Attention