1. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 1 Sequential Logic Implementation zModels for representing sequential circuits yFinite-state machines (Moore and Mealy) yRepresentation of memory (states) yChanges in state (transitions) zDesign procedure yState diagrams yState transition table yNext state functions

2. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 2 RSRSRS DQDQDQDQ OUT1OUT2OUT3OUT4 CLK IN1IN2IN3IN4 RS "0" Registers zCollections of flip-flops with similar controls and logic yStored values somehow related (e.g., form binary value) yShare clock, reset, and set lines ySimilar logic at each stage zExamples yShift registers yCounters

3. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 3 DQDQDQDQ IN OUT1OUT2OUT3OUT4 CLK Shift Register zHolds samples of input yStore last 4 input values in sequence y4-bit shift register:

4. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 4 Shift Register Verilog module shift_reg (out4, out3, out2, out1, in, clk); output out4, out3, out2, out1; input in, clk; reg out4, out3, out2, out1; always @(posedge clk) begin out4 <= out3; out3 <= out2; out2 <= out1; out1 <= in; end endmodule

5. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 5 Shift Register Verilog module shift_reg (out, in, clk); output [4:1] out; input in, clk; reg [4:1] out; always @(posedge clk) begin out <= {out[3:1], in}; end endmodule

6. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 6 clear sets the register contents and output to 0 s1 and s0 determine the shift function s0s1function 00hold state 01shift right 10shift left 11load new input left_in left_out right_out clear right_in output input s0 s1 clock Universal Shift Register zHolds 4 values ySerial or parallel inputs ySerial or parallel outputs yPermits shift left or right yShift in new values from left or right

7. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 7 Nth cell s0 and s1 control mux 0123 D Q CLK CLEAR Q[N-1] (left) Q[N+1] (right) Input[N] to N-1th cell to N+1th cell clears0s1new value 1––0 000output 001output value of FF to left (shift right) 010output value of FF to right (shift left) 011input Design of Universal Shift Register zConsider one of the four flip-flops yNew value at next clock cycle:

8. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 8 Universal Shift Register Verilog module univ_shift (out, lo, ro, in, li, ri, s, clr, clk); output [3:0] out; output lo, ro; input [3:0] in; input [1:0] s; input li, ri, clr, clk; reg [3:0] out; assign lo = out[3]; assign ro = out[0]; always @(posedge clk or clr) begin if (clr) out <= 0; else case (s) 3: out <= in; 2: out <= {out[2:0], ri}; 1: out <= {li, out[3:1]}; 0: out <= out; endcase end endmodule

9. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 9 parallel inputs parallel outputs serial transmission Shift Register Application zParallel-to-serial conversion for serial transmission

10. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 10 DQDQDQDQ IN OUT1OUT2OUT3OUT4 CLK OUT Pattern Recognizer zCombinational function of input samples yIn this case, recognizing the pattern 1001 on the single input signal

11. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 11 DQDQDQDQ IN OUT1OUT2OUT3OUT4 CLK DQDQDQDQ IN OUT1OUT2OUT3OUT4 CLK Counters zSequences through a fixed set of patterns yIn this case, 1000, 0100, 0010, 0001 yIf one of the patterns is its initial state (by loading or set/reset) zMobius (or Johnson) counter yIn this case, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000

12. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 12 Binary Counter zLogic between registers (not just multiplexer) yXOR decides when bit should be toggled yAlways for low-order bit, only when first bit is true for second bit, and so on

13. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 13 Binary Counter Verilog module shift_reg (out4, out3, out2, out1, clk); output out4, out3, out2, out1; input in, clk; reg out4, out3, out2, out1; always @(posedge clk) begin out4 <= (out1 & out2 & out3) ^ out4; out3 <= (out1 & out2) ^ out3; out2 <= out1 ^ out2; out1 <= out1 ^ 1b’1; end endmodule

14. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 14 Binary Counter Verilog module shift_reg (out4, out3, out2, out1, clk); output [4:1] out; input in, clk; reg [4:1] out; always @(posedge clk) out <= out + 1; endmodule

15. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 15 EN D C B A LOAD CLK CLR RCO QD QC QB QA (1) Low order 4-bits = 1111 (2) RCO goes high (3) High order 4-bits are incremented Four-bit Binary Synchronous Up-Counter zStandard component with many applications yPositive edge-triggered FFs w/ sync load and clear inputs yParallel load data from D, C, B, A yEnable inputs: must be asserted to enable counting yRCO: ripple-carry out used for cascading counters xhigh when counter is in its highest state 1111 ximplemented using an AND gate

16. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 16 EN D C B A LOAD CLK CLR RCO QD QC QB QA "1" "0" "0" "0" EN D C B A LOAD CLK CLR RCO QD QC QB QA "1" "0" "1" "1" "0" Offset Counters zStarting offset counters – use of synchronous load ye.g., 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1111, 0110,... zEnding offset counter – comparator for ending value ye.g., 0000, 0001, 0010,..., 1100, 1101, 0000 zCombinations of the above (start and stop value)

17. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 17 Abstraction of State Elements zDivide circuit into combinational logic and state zLocalize feedback loops and make it easy to break cycles zImplementation of storage elements leads to various forms of sequential logic Combinational Logic Storage Elements Outputs State OutputsState Inputs Inputs

18. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 18 Forms of Sequential Logic zAsynchronous sequential logic – state changes occur whenever state inputs change (elements may be simple wires or delay elements) zSynchronous sequential logic – state changes occur in lock step across all storage elements (using a periodic waveform - the clock) Clock

19. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 19 In = 0 In = 1 In = 0In = 1 100 010 110 111 001 Finite State Machine Representations zStates: determined by possible values in sequential storage elements zTransitions: change of state zClock: controls when state can change by controlling storage elements zSequential Logic ySequences through a series of states yBased on sequence of values on input signals yClock period defines elements of sequence

20. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 20 Example Finite State Machine Diagram zCombination lock from first lecture reset S3 closed mux=C1 equal & new not equal & new not new S1S2OPEN ERR closed mux=C2 equal & new closed mux=C3 equal & new open

21. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 21 Can Any Sequential System be Represented with a State Diagram? zShift Register yInput value shown on transition arcs yOutput values shown within state node 100 110 111 011 101010 000 001 0 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 DQDQDQ IN OUT1OUT2OUT3 CLK

22. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 22 010 100 110 011 001 000 101 111 3-bit up-counter Counters are Simple Finite State Machines zCounters yProceed thru well-defined state sequence in response to enable zMany types of counters: binary, BCD, Gray-code y3-bit up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000,... y3-bit down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111,...

23. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 23 Verilog Upcounter module binary_cntr (q, clk) inputs clk; outputs [2:0] q; reg [2:0] q; reg [2:0] p; always @(q) //Calculate next state case (q) 3’b000: p = 3’b001; 3’b001: p = 3’b010; … 3’b111: p = 3’b000; endcase always @(posedge clk) //next becomes current state q <= p; endmodule

24. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 24 How Do We Turn a State Diagram into Logic? zCounter yThree flip-flops to hold state yLogic to compute next state yClock signal controls when flip-flop memory can change xWait long enough for combinational logic to compute new value xDon't wait too long as that is low performance

25. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 25 FSM Design Procedure zStart with counters ySimple because output is just state ySimple because no choice of next state based on input zState diagram to state transition table yTabular form of state diagram yLike a truth-table zState encoding yDecide on representation of states yFor counters it is simple: just its value zImplementation yFlip-flop for each state bit yCombinational logic based on encoding

26. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 26 010 100 110 011 001 000 101 111 3-bit up-counter current state next state 00000011 10010102 20100113 30111004 41001015 51011106 61101117 71110000 FSM Design Procedure: State Diagram to Encoded State Transition Table zTabular form of state diagram zLike a truth-table (specify output for all input combinations) zEncoding of states: easy for counters – just use value

27. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 27 C3C2C1N3N2N1 000001 001010 010011 011100 100101 101110 110111 111000 N1:= C1' N2:= C1C2' + C1'C2 := C1 xor C2 N3:= C1C2C3' + C1'C3 + C2'C3 := C1C2C3' + (C1' + C2')C3 := (C1C2) xor C3 notation to show function represent input to D-FF Implementation zD flip-flop for each state bit zCombinational logic based on encoding 0 000100011 11011101 C1 C2 C3 N3 01100110 10011001 C1 C2 C3 N2 1010 C1 C2 C3 N1

28. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 28 D Q Q Implementation (cont'd) zProgrammable Logic Building Block for Sequential Logic yMacro-cell: FF + logic xD-FF xTwo-level logic capability like PAL (e.g., 8 product terms)

29. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 29 InC1C2C3N1N2N3 0000000 0001000 0010001 0011001 0100010 0101010 0110011 0111011 1000100 1001100 1010101 1011101 1100110 1101110 1110111 1111111 N1:= In N2:= C1 N3:= C2 Another Example zShift Register yInput determines next state 100 110 111 011 101010 000 001 0 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 DQDQDQ IN OUT1OUT2OUT3 CLK

30. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 30 More Complex Counter Example zComplex Counter yRepeats five states in sequence yNot a binary number representation zStep 1: Derive the state transition diagram yCount sequence: 000, 010, 011, 101, 110 zStep 2: Derive the state transition table from the state transition diagram Present StateNext State CBAC+B+A+ 000010 001––– 010011 011101 100––– 101110 110000 111––– note the don't care conditions that arise from the unused state codes 010 000110 101 011

31. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 31 C+ := A B+ := B' + A'C' A+ := BC' More Complex Counter Example (cont’d) zStep 3: K-maps for Next State Functions 0 00X100X1 0XX10XX1 A B C C+1 11X011X0 0XX10XX1 A B C B+ 01X101X1 0XX00XX0 A B C A+

32. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 32 Self-Starting Counters (cont’d) zRe-deriving state transition table from don't care assignment 0101 A B C C+ 1 11101110 01010101 A B C B+ 0101010100 A B C A+ Present StateNext State CBAC+B+A+ 000010 001110 010011 011101 100010 101110 110000 111100 010 000110 101 011 001111 100

33. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 33 Self-Starting Counters zStart-up States yAt power-up, counter may be in an unused or invalid state yDesigner must guarantee it (eventually) enters a valid state zSelf-starting Solution yDesign counter so that invalid states eventually transition to a valid state yMay limit exploitation of don't cares implementation on previous slide 010 000110 101 011 001111 100 010 000110 101 011 001 111 100

34. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 34 State Machine Model zValues stored in registers represent the state of the circuit zCombinational logic computes: yNext state xFunction of current state and inputs yOutputs xFunction of current state and inputs (Mealy machine) xFunction of current state only (Moore machine) Inputs Outputs Next State Current State output logic next state logic

35. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 35 Inputs Outputs Next State Current State output logic next state logic State Machine Model (cont’d) zStates: S 1, S 2,..., S k zInputs: I 1, I 2,..., I m zOutputs: O 1, O 2,..., O n zTransition function: F s (S i, I j ) zOutput function: F o (S i ) or F o (S i, I j )

36. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 36 Example: Ant Brain (Ward, MIT) zSensors: L and R antennae, 1 if in touching wall zActuators: F - forward step, TL/TR - turn left/right slightly zGoal: find way out of maze zStrategy: keep the wall on the right

37. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 37 Ant Brain

38. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 38 A: Following wall, touching Go forward, turning left slightly B: Following wall, not touching Go forward, turning right slightly C: Break in wall Go forward, turning right slightly D: Hit wall again Back to state A E: Wall in front Turn left until... F:...we are here, same as state B G: Turn left until... LOST: Forward until we touch something Ant Behavior

39. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 39 Designing an Ant Brain zState Diagram R’ C (TR, F) R’L’ R’ B (TR, F) L’ R’ L R A (TL, F) R L’ R L + R E/G (TL) L + R LOST (F) L’ R’

40. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 40 Synthesizing the Ant Brain Circuit zEncode States Using a Set of State Variables yArbitrary choice - may affect cost, speed zUse Transition Truth Table yDefine next state function for each state variable yDefine output function for each output zImplement next state and output functions using combinational logic y2-level logic (ROM/PLA/PAL) yMulti-level logic yNext state and output functions can be optimized together

41. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 41 Transition Truth Table zUsing symbolic states and outputs LOST (F) E/G (TL) A (TL, F) B (TR, F) C (TR, F) R’ L’ R’ R L R L’ R L + R L’ R’ stateLRnext stateoutputs LOST00LOSTF LOST–1E/GF LOST1– E/GF A00BTL, F A01ATL, F A1– E/GTL, F B– 0CTR, F B– 1ATR, F...............

42. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 42 stateLRnext stateoutputs X,Y,ZX', Y', Z'FTRTL 0 0 0000 0 0100 0 0 0010 0 1100............... 0 1 0000 1 1101 0 1 0010 1 0101 0 1 0100 0 1101 0 1 0110 0 1101 0 1 1001 0 0110 0 1 1010 1 0110............... LOST- 000 E/G- 001 A- 010 B- 011 C- 100 it now remains to synthesize these 6 functions Synthesis z5 states : at least 3 state variables required (X, Y, Z) yState assignment (in this case, arbitrarily chosen)

43. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 43 stateinputsnext stateoutputs X,Y,ZL RX +,Y +,Z + FTRTL 0 0 0000 0 0100 0 0 0-10 0 1100 0 0 01-0 0 1100 0 0 1000 1 1001 0 0 1-10 1 0001 0 0 11-0 1 0001 0 1 0000 1 1101 0 1 0010 1 0101 0 1 01-0 0 1101 0 1 1-01 0 0110 0 1 1-10 1 0110 1 0 0-01 0 0110 1 0 0-10 1 0110 e.g. TR = X + Y Z X + = X R’ + Y Z R’ = R’ TR Synthesis of Next State and Output Functions

44. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 44 Circuit Implementation zOutputs are a function of the current state only - Moore machine LRLR F TR TL Next State Current State output logic next state logic X+X+ Y+Y+ Z+Z+ XYZ

45. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 45 Verilog Sketch module ant_brain (F, TR, TL, L, R) inputs L, R; outputs F, TR, TL; reg X, Y, Z; assign F = function(X, Y, Z, L, R); assign TR = function(X, Y, Z, L, R); assign TL = function(X, Y, Z, L, R); always @(posedge clk) begin X <= function (X, Y, Z, L, R); Y <= function (X, Y, Z, L, R); Z <= function (X, Y, Z, L, R); end endmodule

46. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 46 Ant is in deep trouble if it gets in this state Don’t Cares in FSM Synthesis zWhat happens to the "unused" states (101, 110, 111)? zExploited as don't cares to minimize the logic yIf states can't happen, then don't care what the functions do yif states do happen, we may be in trouble 000 (F) 001 (TL) 010 (TL, F) 011 (TR, F) 100 (TR, F) R’ L’ R’ R L R L’ R L + R L’ R’ 111 101 110

47. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 47 State Minimization zFewer states may mean fewer state variables zHigh-level synthesis may generate many redundant states zTwo state are equivalent if they are impossible to distinguish from the outputs of the FSM, i. e., for any input sequence the outputs are the same zTwo conditions for two states to be equivalent: y1) Output must be the same in both states y2) Must transition to equivalent states for all input combinations

48. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 48 Ant Brain Revisited zAny equivalent states? LOST (F) E/G (TL) A (TL, F) B (TR, F) C (TR, F) R’ L’ R’ R L R L’ R L + R L’ R’

49. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 49 New Improved Brain zMerge equivalent B and C states zBehavior is exactly the same as the 5-state brain zWe now need only 2 state variables rather than 3 LOST (F) E/G (TL) A (TL, F) B/C (TR, F) R’ L’ R’ R L L’ R L + R L’ R’

50. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 50 stateinputs next stateoutputs X,YL RX',Y'FTRTL 0 0000 0100 0 0-10 1100 0 01-0 1100 0 1001 1001 0 1-10 1001 0 11-0 1001 1 0001 1101 1 0011 0101 1 01-0 1101 1 1-01 1110 1 1-11 0110 New Brain Implementation 10111011101110111011101110111011 X F Y R L 00100010001000100010001000100010 X TR Y R L 01010101010101010101010101010101 X TL Y R L 01110011001000100111001100100010 X X+ Y R L 01111000100110110111100010011011 X Y+ Y R L

51. CS 150 - Spring 2007 – Lec #6: Moore and Mealy Machines - 51 Sequential Logic Implementation Summary zModels for representing sequential circuits yAbstraction of sequential elements yFinite state machines and their state diagrams yInputs/outputs yMealy, Moore, and synchronous Mealy machines zFinite state machine design procedure yDeriving state diagram yDeriving state transition table yDetermining next state and output functions yImplementing combinational logic