1. George Mason University ECE 448 – FPGA and ASIC Design with VHDL Overview of Modern FPGAs ECE 448 Lecture 14

2. 2ECE 448 – FPGA and ASIC Design with VHDL Resources Clive “Max” Maxfield, The Design Warrior’s Guide to FPGAs, Elsevier, 2004.

3. 3ECE 448 – FPGA and ASIC Design with VHDL Resources Xcell Journal available for FREE on line @ http://www.xilinx.com/publications/xcellonline/ Electronic Engineering Journal available for FREE by e-mail after subscribing @ http://www.eejournal.com/subscribe http://www.eejournal.com/subscribe or on the web @ http://www.eejournal.com/design/fpga

4. 4ECE 448 – FPGA and ASIC Design with VHDL FPGA Vendors & Families

5. 5 Major FPGA Vendors SRAM-based FPGAs Xilinx, Inc. Altera Corp. Atmel Lattice Semiconductor Flash & antifuse FPGAs Actel Corp. Quick Logic Corp. Share about 90% of the market

6. 6ECE 448 – FPGA and ASIC Design with VHDL Xilinx FPGA Families Old families XC3000, XC4000, XC5200 Old 0.5µm, 0.35µm and 0.25µm technology. Not recommended for modern designs. High-performance families Virtex (220 nm) Virtex-E, Virtex-EM (180 nm) Virtex-II (130 nm) Virtex-II PRO (130 nm) Virtex-4 (90 nm) Virtex-5 (65 nm) Virtex-6 (40 nm) Low Cost Family Spartan/XL – derived from XC4000 Spartan-II – derived from Virtex Spartan-IIE – derived from Virtex-E Spartan-3 (90 nm) Spartan-3E (90 nm) – logic optimized Spartan-3A (90 nm) – I/O optimized Spartan-3AN (90 nm) – non-volatile, Spartan-3A DSP (90 nm) – DSP optimized Spartan-6 (45 nm)

7. TechnologyLow-costHigh- performance 120/150 nmVirtex 2, 2 Pro 90 nmSpartan 3Virtex 4 65 nmVirtex 5 45 nmSpartan 6 40 nmVirtex 6 Xilinx FPGA Devices

8. Altera FPGA Devices TechnologyLow-costMid-rangeHigh- performanc e 130 nmCycloneStratix 90 nmCyclone IIStratix II 65 nmCyclone IIIArria IStratix III 40 nmCyclone IVArria IIStratix IV

9. ECE 448 – FPGA and ASIC Design with VHDL LUTs & ALUTs

10. 10ECE 448 – FPGA and ASIC Design with VHDL 4-bit LUTs vs. 6-bit LUTs 6-bit LUTs introduced in Virtex 5

11. 11 Major Differences between Xilinx Families Number of CLB slices per CLB Number of LUTs per CLB slice Look-Up Tables Spartan 3 Virtex 4 Virtex 5, Virtex 6, Spartan 6 4-input6-input 4 2 2 4

12. 12 Major Differences between Xilinx Families Maximum Shift Register Size per LUT Maximum Single-Port Memory Size per LUT Number of adder stages per CLB slice Spartan 3 Virtex 4 Virtex 5, Virtex 6, Spartan 6 16 x 164 x 1 16 bits 2 32 bits 4

13. Altera Cyclone III Logic Element (LE) – Normal Mode

14. 14 Altera Stratix III Adaptive Logic Modules (ALM) – Normal Mode

15. ECE 448 – FPGA and ASIC Design with VHDL FPGA Embedded Resources

16. ECE 448 – FPGA and ASIC Design with VHDL Embedded Multipliers

18. 18 ECE 448 – FPGA and ASIC Design with VHDL Multipliers in Spartan 3 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

19. 19 Number of Multipliers per Spartan 3 Device

20. 20 Combinational and Registered Multiplier ECE 448 – FPGA and ASIC Design with VHDL

21. 21 ECE 448 – FPGA and ASIC Design with VHDL Dedicated Multiplier Block

22. Cyclone II

23. Embedded Multiplier Block Overview Each Cyclone II has one to three columns of embedded multipliers. Each embedded multiplier can be configured to support  One 18 x 18 multiplier  Two 9 x 9 multipliers

24. Number of Embedded Multipliers

25. Multiplier Block Architecture

26. Two Multiplier Types Two 9x9 multiplier 18x18 multiplier

27. Multiplier Stage Signals signa and signb are used to identify the signed and unsigned inputs.

28. 28 3 Ways to Use Dedicated Hardware Three (3) ways to use dedicated (embedded) hardware –Inference –Instantiation –CoreGen in Xilinx MegaWizard Plug-In Manager in Altera

29. ECE 448 – FPGA and ASIC Design with VHDL DSP Units

30. 30 Xilinx XtremeDSP Starting with Virtex 4 family, Xilinx introduced DSP48 block for high-speed DSP on FPGAs Essentially a multiply-accumulate core with many other features Now also in Spartan-3A, Spartan 6, Virtex 5, and Virtex 6

31. 31 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Multiplier-Accumulator - MAC

32. 32 Mathematical Functions DSP 48 can perform mathematical functions such as: Add/Subtract Accumulate Multiply Multiply-Accumulate Multiplexer Barrel Shifter Counter Divide (multi-cycle) Square Root (multi-cycle) Can also create filters such as: Serial FIR Filter (Xilinx calls this MACC filters) Parallel FIR Filter Semi-Parallel FIR Filter Multi-rate FIR Filters

33. 33 DSP48 Slice: Virtex 4

34. 34 Simplified Form of DSP48 Adder Out = (Z ± (X + Y + CIN))

35. 35 Choosing Inputs to DSP Adder P = Adder Out = (Z ± (X + Y + CIN))

36. 36 DSP48E Slice : Virtex5

37. 37 New in Virtex 5 Compared to Virtex 4

38. 38 Xilinx DSP48

39. Stratix III DSP Unit

40. ECE 448 – FPGA and ASIC Design with VHDL Embedded Memories

41. 41 Memory Types Memory RAMROM Single portDual port With asynchronous read With synchronous read Memory

42. 42 Memory Types in Xilinx Memory Distributed (MLUT-based) Block RAM-based (BRAM-based) InferredInstantiated Memory Manually Using Core Generator

43. 43 Memory Types in Altera Memory Distributed (ALUT-based, Stratix III onwards) Memory block-based Inferred Instantiated Memory Manually Using MegaWizard Plug-In Manager Small size (512) Large size (144K, 512K) Medium size (4K, 9K, 20K)

44. The embedded memory structure consists of columns of M4K memory blocks that can be configured as RAM, first-in first-out (FIFO) buffers, and ROM Cyclone II Memory Blocks

45. The M4K memory blocks support the following modes:  Single-port RAM (RAM:1-Port)  Simple dual-port RAM (RAM: 2-Port)  True dual-port RAM (RAM:2-Port)  Tri-port RAM (RAM:3-Port)  Single-port ROM (ROM:1-Port)  Dual-port ROM (ROM:2-Port) Memory Modes

46. Single-Port ROM The address lines of the ROM are registered The outputs can be registered or unregistered A.mif file is used to initialize the ROM contents

47. Stratix II TriMatrix Memory

49. Stratix III & Stratix IV TriMatrix Memory

50. Stratix II & III Shift-Register Memory Configuration

51. 51ECE 448 – FPGA and ASIC Design with VHDL Supply Voltage

52. 52ECE 448 – FPGA and ASIC Design with VHDL Change in Supply Voltages Year Technology (nm)Core Supply Voltage (V) 1998 3503.3 1999 250 2.5 2000 180 1.8 2001 150 1.5 2003 130 1.2 2008 65 1.0 2009 40 0.9

53. 53ECE 448 – FPGA and ASIC Design with VHDL Gigabit Transceivers

54. 54 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Using a Bus to Communicate Between Devices

55. 55ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Using High-Speed Tranceivers to Communicate Between Devices

56. 56 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Using High-Speed Tranceivers to Communicate Between Devices

57. 57 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Effect of Noise on Single Wire and Differential Pair

58. 58 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Generating a Differential Pair

59. 59 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Multiple Standards for High-Speed Serial Communication Fibre Channel InfiniBand PCI Express (developed by Intel) RapidIO SkyRail (developed by MindSpeed Technologies) 10-gigabit Ethernet

60. 60 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Using FPGA to Interface Between Multiple Standards

61. 61 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Ganging Multiple Transceivers Together

62. 62 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) An Ideal Signal vs. Signal Seen by Receiver

63. 63 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) The Effects of Transmitting a Series of Identical Bits

64. 64 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Main Elements of the Transceiver Block

65. 65 Recovering Clock Signal

66. 66 Sampling the Incoming Signal

67. 67ECE 448 – FPGA and ASIC Design with VHDL Embedded Microprocessors

68. 68ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Embedded Microprocessor Cores

69. 69ECE 448 – FPGA and ASIC Design with VHDL Virtex-II Pro Architecture24 6 1 5 3 Features: 1.Processor Block 2.RocketIO Multi-Gigabit Transceivers 3.CLB and Configurable Logic 4.SelectIO-Ultra 5.Digital Clock Managers 6.Multipliers and Block SelectRAM

70. 70ECE 448 – FPGA and ASIC Design with VHDL

71. 71ECE 448 – FPGA and ASIC Design with VHDL PowerPC Cores PowerPC System

72. 72ECE 448 – FPGA and ASIC Design with VHDL Embedded Development Kit (EDK) Processor IP, Microprocessor Peripheral Description Files System Constraint File PlatGen Data2MEM Download to FPGA Libraries Microprocessor Software Specification File Microprocessor Hardware Specification File Executable Linker C / C++ Code Compiler Bitstream VHDL / Verilog Hardware Flow ISE / Xflow Software Flow Synthesizer Object Files EDIF IP Netlists LibGen