1. EET 1131 Unit 12 Shift Registers
Read Kleitz, Chapter 13, skipping Sections 13-6 and
Homework #12 and Lab #12 due next week.
Quiz next week.
-Handouts: Comparison slide (Slide #2), and timing diagrams in practiceShiftRegs.docx.
-FIRE UP MULTISIM.
-Collect HW & Lab, and do Quiz.

2. Comparison of Counters & Shift Registers
4-bit Asynchronous Counter:
4-bit Synchronous Counter:
4-bit Shift Register:
-Actually more common to use D-flip-flops for a shift reg (as shown on Slide #4), rather than J-K. 2

3. Basic Shift Register Operations
A shift register is a digital circuit with two basic functions: data storage and data movement. Some basic data movements are illustrated here.
Data in
Data in
Data out
Data out
Data in
Data out
Serial in/shift right/serial out
Serial in/shift left/serial out
Parallel in/serial out
Data in
-Not very glamorous, but important.
-After this slide, quickly jump to UART slide below, and then come back here.
Data in
Data out
Data out
Serial in/parallel out
Parallel in/parallel out
Rotate right
Rotate left

4. Serial-in/Serial out Shift Register
Shift registers are available in IC form or can be constructed from discrete flip-flops, as shown here with a five-bit serial-in serial-out register.
Each clock pulse will move an input bit to the next flip-flop. For example, a 1 is shown as it moves across. 1 1 1 1 1 1
-Demo with Multisim file shiftReg.ms10.
CLK
CLK
CLK
CLK
CLK

5. A Basic Application
One application of shift registers is conversion of serial data to parallel form.
For example, assume the binary number 1011 is loaded sequentially, one bit at each clock pulse.
After 4 clock pulses, the data is available at the parallel output.
CLK
CLK
CLK
CLK

6. The 74164 is an 8-bit serial in/parallel out shift register.
The Shift Register
The is an 8-bit serial in/parallel out shift register.
MR is an input, so it really
belongs on the left side with
the other inputs instead of on
the bottom with the outputs.
As with counters, we usually show LSB on left and MSB on right. Data is shifted into Q0.
One of the two serial data inputs may be used as an active HIGH enable to gate the other input. If no enable is needed, the other serial input can be connected to VCC. The has an active LOW asynchronous clear (MR). Data is entered on the rising edge of the clock.

7. Waveforms for the 74164
Sample waveforms for the are shown. Notice that B acts as an active HIGH enable for the data on A. MR
DSa
Serial inputs
DSb
CLK Q0 Q1 Q2 Q3
Do practice sheet for
Outputs Q4 Q5 Q6 Q7
Clear
Clear

8. The 74165 is an 8-bit parallel in/serial out shift register.
The Shift Register
The is an 8-bit parallel in/serial out shift register.
-This one’s harder to visualize because you can only see the bits when they pop out on the right-hand end (Q7). Before they get there, they march unseen through the register.
-LOAD is asynchronous.
Data is loaded asynchronously when PL is LOW. Data is shifted through the register synchronously when PL is HIGH and a rising clock edge occurs.

9. Universal Shift Register
A universal shift register has both serial and parallel input and output capability. The is an example of a 4-bit bidirectional universal shift register.
S1 S0 Mode
Hold
Shift right
Shift left
Parallel load (synchronous)
Sample waveforms on the following slide…

10. Universal Shift Register
Do practice sheet for

11. Some Shift Register Chips
74164 (8-bit serial in/parallel out)
74165 (8-bit parallel in/serial out)
74194 (4-bit bidirectional universal)
74195 (4-bit parallel access)

12. Example Solution Shift Register Applications
Shift registers can be used to delay a digital signal by a predetermined amount.
An 8-bit serial in/serial out shift register has a 40 MHz clock. What is the total delay through the register?
Example
Solution
The delay for each clock is 1/40 MHz = 25 ns
25 ns
The total delay is 8 x 25 ns = 200 ns
= 200 ns

13. Shift Register Applications
Data bus
A UART (Universal Asynchronous Receiver Transmitter) is a serial-to-parallel converter and a parallel to serial converter.
UARTs are commonly used in small systems where one device must communicate with another. Parallel data is converted to asynchronous serial form and transmitted. The serial data format is:
CLK
CLK
Serial data out
Serial data in
Start
Bit (0)
Stop Bits (1)

14. Cascading Shift Registers
Most shift register chips are 4-bit or 8-bit shift registers.
To get larger shift registers, you can cascade two or more chips together.
For a circuit in Lab #12 you’ll need to think about how to do this. 14

15. Shift Counters
Shift registers can form useful counters by recirculating a pattern of 0’s and 1’s. Two important shift counters are the ring shift counter and the Johnson shift counter.

16. Ring Shift Counter
The ring shift counter can be implemented with either D flip-flops or J-K flip-flops.
Here is a 4-bit ring shift counter constructed from a series of D flip-flops. Notice the feedback.
It can also be implemented with J-K flip flops.

17. Ring Shift Counter
Redrawing the ring shift counter (without the clock shown) shows why it is a “ring”.
In practical applications, the counter is preloaded with the desired pattern (usually a single 0 or 1).
It has n states, where n = number of flip-flops.

18. Ring Shift Counter
A common pattern for a ring shift counter is to load it with a single 1 or a single 0. The waveforms shown here are for an 8-bit ring shift counter with a single 1.
-What is the count sequence of this “counter”? What is its MOD?
-Demo with Multisim file shiftCounter.ms10.

19. Johnson Shift Counter
The Johnson shift counter can be made with a series of D flip-flops
… or with a series of J-K flip flops. Here Q3 and Q3 are fed back to the J and K inputs with a “twist”.

20. Johnson Shift Counter
Redrawing the same Johnson shift counter (without the clock shown) illustrates why it is sometimes called as a “twisted-ring” counter.
“twist”
-Demo by modifying Multisim to change from ring shift counter to Johnson shift counter.

21. Question Johnson Shift Counter
The Johnson shift counter is useful when you need a sequence that changes by only one bit at a time but it has a limited number of states (2n, where n = number of stages).
The first five counts for a 4-bit Johnson counter that is initially cleared are: CLK Q0 Q1 Q2 Q3 1 2 3 4 5 6 7
What is its count sequence? What is its MOD?
Question
What are the remaining 3 states?

22. Keyboard Encoder
The keyboard encoder is an example of where a ring counter is used in a small system to encode a key press.
Two shift registers are connected as an 8-bit ring counter preloaded with a single 0. As the 0 circulates in the ring counter, it “scans” the keyboard looking for any row that has a key closure. When one is found, a corresponding column line is connected to that row line. The combination of the unique column and row lines identifies the key. The schematic is shown on the following slide…

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