1. ECE 667 - Synthesis & Verification 1 ECE 667 ECE 667 Synthesis and Verification of Digital Systems Retiming

2. ECE 667 - Synthesis & Verification 2 Retiming Outline: Problem – sequential synthesis Formulation Retiming algorithm

3. ECE 667 - Synthesis & Verification 3 Optimizing Sequential Circuits by Retiming Gate-level Netlist Netlist of gates and registers: Various Goals: –Reduce clock cycle time –Reduce area Reduce number of latches (registers) Inputs Outputs

4. ECE 667 - Synthesis & Verification 4 Retiming Problem – –Pure combinational optimization can be myopic since relations across register boundaries are disregarded Solutions – –Retiming: Move register(s) so that clock cycle decreases, or number of registers decreases and input-output behavior is preserved – –Peripheral retiming: Combine retiming with combinational optimization techniques move latches out of the way temporarily optimize larger blocks of combinational logic

5. ECE 667 - Synthesis & Verification 5 Circuit Representation [Leiserson, Rose and Saxe (1983)] Circuit representation: G(V,E,d,w) – –V  set of gates – –E  set of wires – –d(v) = delay of gate/vertex v, (d(v)  0) – –w(e) = number of registers on edge e, (w(e)  0)

6. ECE 667 - Synthesis & Verification 6 Circuit Representation Example: Correlator Circuit  (x, y) = 1 if x=y 0 otherwise Operation delay  3  3 + 7 + 7 Every cycle in the graph has at least one register, i.e., there are no combinational loops. 0 33 0 0 0 0 2 Graph (Directed)7a b+ Host

7. ECE 667 - Synthesis & Verification 7 Preliminaries For a path p : Clock cycle c: For the correlator circuit: c = 13 Can we reduce it to 7 ? How ? Path with w(p)=0 0 33 0 0 0 0 2 7

8. ECE 667 - Synthesis & Verification 8 Movement of registers – –from input to output of a gate or vice versa Does not affect gate functionalities A mathematical definition: retardation – –r: V  Z, an integer vertex labeling – –w r (e) = w(e) + r(v) - r(u) for edge e = (u,v) Basic Operation Retime by 1 Retime by -1

9. ECE 667 - Synthesis & Verification 9 In the example, r(u) = -1, r(v) = -1 results in For a path p: s  t, w r (p) = w(p) + r(t) - r(s) Retardation – –r : V  Z, an integer vertex labeling – –w r (e) = w(e) + r(v) - r(u) for edge e = (u,v) – –A retiming r is legal if w r (e)  0,  e  E (prove it !) Basic Operation vu 0 33 0 0 0 0 2 7 0 v u 0 33 0 1 1 1 7

10. ECE 667 - Synthesis & Verification 10 Retiming for Minimum Clock Cycle Problem Statement: (minimum cycle time) Given G (V, E, d, w), find a legal retiming r so that is minimized Retiming: 2 important matrices Register weight matrix Delay matrix

11. ECE 667 - Synthesis & Verification 11 Retiming for Minimum Clock Cycle W V0 V1 V2 V3 V0V1V2V3 0 2 2 2 0 0 0 0 0 2 0 0 0 2 2 0 c     p, if d(p)   then w(p)  1 D V0 V1 V2 V3 V0V1V2V3 0 3 6 13 13 3 6 13 10 13 3 10 7 10 13 7 W = register path weight matrix (minimum # latches on all paths between u and v) (minimum # latches on all paths between u and v) D = path delay matrix (maximum delay on all paths between u and v) (maximum delay on all paths between u and v) v2 v1 v0 0 33 0 0 0 0 2 7v3 Delays exceeding 7 shown in red

12. ECE 667 - Synthesis & Verification 12 Conditions for Legal Retiming Assume that we are asked to check if a retiming exists for a clock cycle  Legal retiming: w r (e)  0 for all e. Hence w r (e) = w(e) + r(v) - r(u)  0 or r (u) - r (v)  w (e) For all paths p: u  v such that d(p)  , we require w r (p)  1 – –Thus Or take the least w(p) (tightest constraint) r(u)-r(v)  W(u,v)-1 Note: this is independent of the path from u to v, so we just need to apply it to u, v such that D(u,v)  

13. ECE 667 - Synthesis & Verification 13 All constraints in difference-of-2-variable form Related to longest/shortest path problem Solving the Constraints Correlator: Correlator:  = 7 Legal: r(u)-r(v)  w(e) Timing D>7: r(u)-r(v)  W(u,v)-1 W V0 V1 V2 V3 V0V1V2V3 0 2 2 2 0 0 0 0 0 2 0 0 0 2 2 0 V2 v1 v0 0 33 0 0 0 0 2 7v3 D V0 V1 V2 V3 V0V1V2V3 0 3 6 13 13 3 6 13 10 13 3 10 7 10 13 7

14. ECE 667 - Synthesis & Verification 14 Do shortest path on constraint graph: (O(|V| 3 )). A solution exists if and only if there exists no negative weighted cycle. Solving the Constraints Legal: r(u)-r(v)  w(e) Timing D>7: r(u)-r(v)  W(u,v)-1 A solution: A solution: r(v 0 ) = r(v 3 ) = 0, r(v 1 ) = r(v 2 ) = -1 r(1) r(0) r(3)r(2) 0 1 1 1 1 1 0,-1 0,-1 0 02 Constraint graph

15. ECE 667 - Synthesis & Verification 15 Retiming To find the minimum cycle time, do a binary search among the entries of the D matrix (0(  V  3 log  V  )) Retime Retimed correlator: v0 V2 v1 0 33 0 0 0 0 27 Clock cycle = 3+3+7=13 = 3+3+7=13 a b+ Host Clock cycle = 7 a b+ Host W V0 V1 V2 V3 V0V1V2V3 0 2 2 2 0 0 0 0 0 2 0 0 0 2 2 0 D V0 V1 V2 V3 V0V1V2V3 0 3 6 13 13 3 6 13 10 13 3 10 7 10 13 7

16. ECE 667 - Synthesis & Verification 16 1. Relaxation based: – –Repeatedly find critical path; – –retime vertex at end of path by +1 (O(  V  E  log  V  )) 2. Also, Mixed Integer Linear Program formulation Retiming: two more Algorithms +1 u Critical path v

17. ECE 667 - Synthesis & Verification 17 Relaxation Algorithm - Rationale

18. ECE 667 - Synthesis & Verification 18 Relaxation Algorithm

19. ECE 667 - Synthesis & Verification 19 Relaxation Algorithm – step 1 Retime for = 13 Retime for  = 13

20. ECE 667 - Synthesis & Verification 20 Relaxation Algorithm – step 2 Retime for = 13 Retime for  = 13

21. ECE 667 - Synthesis & Verification 21 Relaxation Algorithm – step 3 Retimed for = 13 Retimed for  = 13

22. ECE 667 - Synthesis & Verification 22 Relaxation Algorithm – summary (Retiming for  = 13)

23. ECE 667 - Synthesis & Verification 23 Retiming for Minimum Area (Minimum # Latches) Goal: minimize the number of registers used where a v is a constant for each node v.

24. ECE 667 - Synthesis & Verification 24 Minimize: Minimum Registers - Formulation Subject to: Subject to: w r (e) = w(e) + r(v) - r(u)  0 Reducible to a flow problem