Presentation is loading. Please wait.

Presentation is loading. Please wait.

Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response Greco/Cin-UFPE (Material taken/adapted from Harris’ lecture notes)

Published byCorey Ray Modified over 9 years ago

Similar presentations

Presentation on theme: "Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response Greco/Cin-UFPE (Material taken/adapted from Harris’ lecture notes)"— Presentation transcript:

1 Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response Greco/Cin-UFPE (Material taken/adapted from Harris’ lecture notes)

2 CMOS VLSI Design4: DC and Transient ResponseSlide 2 Outline  DC Response  Logic Levels and Noise Margins  Transient Response  Delay Estimation

3 CMOS VLSI Design4: DC and Transient ResponseSlide 3 Activity 1) If the width of a transistor increases, the current will increasedecreasenot change 2) If the length of a transistor increases, the current will increasedecreasenot change 3) If the supply voltage of a chip increases, the maximum transistor current will increasedecreasenot change 4) If the width of a transistor increases, its gate capacitance will increasedecreasenot change 5) If the length of a transistor increases, its gate capacitance will increasedecreasenot change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increasedecreasenot change

4 CMOS VLSI Design4: DC and Transient ResponseSlide 4 Activity 1) If the width of a transistor increases, the current will increasedecreasenot change 2) If the length of a transistor increases, the current will increasedecreasenot change 3) If the supply voltage of a chip increases, the maximum transistor current will increasedecreasenot change 4) If the width of a transistor increases, its gate capacitance will increasedecreasenot change 5) If the length of a transistor increases, its gate capacitance will increasedecreasenot change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increasedecreasenot change

5 CMOS VLSI Design4: DC and Transient ResponseSlide 5 DC Response  DC Response: V out vs. V in for a gate  Ex: Inverter –When V in = 0 -> V out = V DD –When V in = V DD -> V out = 0 –In between, V out depends on transistor size and current –By KCL, must settle such that I dsn = |I dsp | –We could solve equations –But graphical solution gives more insight

6 CMOS VLSI Design4: DC and Transient ResponseSlide 6 Transistor Operation  Current depends on region of transistor behavior  For what V in and V out are nMOS and pMOS in –Cutoff? –Linear? –Saturation?

7 CMOS VLSI Design4: DC and Transient ResponseSlide 7 nMOS Operation CutoffLinearSaturated V gsn <V gsn > V dsn < V gsn > V dsn >

8 CMOS VLSI Design4: DC and Transient ResponseSlide 8 nMOS Operation CutoffLinearSaturated V gsn < V tn V gsn > V tn V dsn < V gsn – V tn V gsn > V tn V dsn > V gsn – V tn

9 CMOS VLSI Design4: DC and Transient ResponseSlide 9 nMOS Operation CutoffLinearSaturated V gsn < V tn V gsn > V tn V dsn < V gsn – V tn V gsn > V tn V dsn > V gsn – V tn V gsn = V in V dsn = V out

10 CMOS VLSI Design4: DC and Transient ResponseSlide 10 nMOS Operation CutoffLinearSaturated V gsn < V tn V in < V tn V gsn > V tn V in > V tn V dsn < V gsn – V tn V out < V in - V tn V gsn > V tn V in > V tn V dsn > V gsn – V tn V out > V in - V tn V gsn = V in V dsn = V out

11 CMOS VLSI Design4: DC and Transient ResponseSlide 11 pMOS Operation CutoffLinearSaturated V gsp >V gsp < V dsp > V gsp < V dsp <

12 CMOS VLSI Design4: DC and Transient ResponseSlide 12 pMOS Operation CutoffLinearSaturated V gsp > V tp V gsp < V tp V dsp > V gsp – V tp V gsp < V tp V dsp < V gsp – V tp

13 CMOS VLSI Design4: DC and Transient ResponseSlide 13 pMOS Operation CutoffLinearSaturated V gsp > V tp V gsp < V tp V dsp > V gsp – V tp V gsp < V tp V dsp < V gsp – V tp V gsp = V in - V DD V dsp = V out - V DD V tp < 0

14 CMOS VLSI Design4: DC and Transient ResponseSlide 14 pMOS Operation CutoffLinearSaturated V gsp > V tp V in > V DD + V tp V gsp < V tp V in < V DD + V tp V dsp > V gsp – V tp V out > V in - V tp V gsp < V tp V in < V DD + V tp V dsp < V gsp – V tp V out < V in - V tp V gsp = V in - V DD V dsp = V out - V DD V tp < 0

15 CMOS VLSI Design4: DC and Transient ResponseSlide 15 I-V Characteristics  Make pMOS is wider than nMOS such that  n =  p

16 CMOS VLSI Design4: DC and Transient ResponseSlide 16 Current vs. V out, V in

17 CMOS VLSI Design4: DC and Transient ResponseSlide 17 Load Line Analysis  For a given V in : –Plot I dsn, I dsp vs. V out –V out must be where |currents| are equal in

18 CMOS VLSI Design4: DC and Transient ResponseSlide 18 Load Line Analysis  V in = 0

19 CMOS VLSI Design4: DC and Transient ResponseSlide 19 Load Line Analysis  V in = 0.2V DD

20 CMOS VLSI Design4: DC and Transient ResponseSlide 20 Load Line Analysis  V in = 0.4V DD

21 CMOS VLSI Design4: DC and Transient ResponseSlide 21 Load Line Analysis  V in = 0.6V DD

22 CMOS VLSI Design4: DC and Transient ResponseSlide 22 Load Line Analysis  V in = 0.8V DD

23 CMOS VLSI Design4: DC and Transient ResponseSlide 23 Load Line Analysis  V in = V DD

24 CMOS VLSI Design4: DC and Transient ResponseSlide 24 Load Line Summary

25 CMOS VLSI Design4: DC and Transient ResponseSlide 25 DC Transfer Curve  Transcribe points onto V in vs. V out plot

26 CMOS VLSI Design4: DC and Transient ResponseSlide 26 Operating Regions  Revisit transistor operating regions RegionnMOSpMOS A B C D E

27 CMOS VLSI Design4: DC and Transient ResponseSlide 27 Operating Regions  Revisit transistor operating regions RegionnMOSpMOS ACutoffLinear BSaturationLinear CSaturation DLinearSaturation ELinearCutoff

28 CMOS VLSI Design4: DC and Transient ResponseSlide 28 Beta Ratio  If  p /  n  1, switching point will move from V DD /2  Called skewed gate  Other gates: collapse into equivalent inverter

29 CMOS VLSI Design4: DC and Transient ResponseSlide 29 Noise Margins  How much noise can a gate input see before it does not recognize the input?

30 CMOS VLSI Design  By definition, V IH and V IL are the operational points of the inverter where 4: DC and Transient ResponseSlide 30 A high gain (g) is desirable

31 CMOS VLSI Design4: DC and Transient ResponseSlide 31 Logic Levels  To maximize noise margins, select logic levels at

32 CMOS VLSI Design4: DC and Transient ResponseSlide 32 Logic Levels  To maximize noise margins, select logic levels at –unity gain point of DC transfer characteristic

33 CMOS VLSI Design4: DC and Transient ResponseSlide 33 Transient Response  DC analysis tells us V out if V in is constant  Transient analysis tells us V out (t) if V in (t) changes –Requires solving differential equations  Input is usually considered to be a step or ramp –From 0 to V DD or vice versa

34 CMOS VLSI Design4: DC and Transient ResponseSlide 34 Inverter Step Response  Ex: find step response of inverter driving load cap

35 CMOS VLSI Design4: DC and Transient ResponseSlide 35 Inverter Step Response  Ex: find step response of inverter driving load cap

36 CMOS VLSI Design4: DC and Transient ResponseSlide 36 Inverter Step Response  Ex: find step response of inverter driving load cap

37 CMOS VLSI Design4: DC and Transient ResponseSlide 37 Inverter Step Response  Ex: find step response of inverter driving load cap

38 CMOS VLSI Design4: DC and Transient ResponseSlide 38 Inverter Step Response  Ex: find step response of inverter driving load cap

39 CMOS VLSI Design4: DC and Transient ResponseSlide 39 Inverter Step Response  Ex: find step response of inverter driving load cap nMOS – “1” transfer is bad

40 CMOS VLSI Design4: DC and Transient ResponseSlide 40 Delay Definitions  t pdr : rising propagation delay –From input to rising output crossing V DD /2 (upper bound)  t pdf : falling propagation delay –From input to falling output crossing V DD /2 (upper bound)  t pd : average propagation delay –t pd = (t pdr + t pdf )/2  t r : rise time –time required for a node to charge from the 10% point to 90% ( 0.1 V DD to 0.9 V DD )  t f : fall time –time required for a node to discharge from 90% to 10% point (0.9 V DD to 0.1 V DD )

41 CMOS VLSI Design4: DC and Transient ResponseSlide 41 T pdr = T pHL T cdf = T pHL trtr tftf Delay Definitions

42 CMOS Inverter Switching Characteristics  Define: –Falling delay t df = delay time with output falling –Rising delay t dr = delay time with output rising

43 43 Trajectory of a n-transistor operating point a.Transistor is Cut off b.Capacitance C L is loaded with VDD a.Applying a V gs =V DD b.V out -> 0,9 to (V DD -T th ) a.V DD -T th -> to 0.1V

44 Slide 44 Fall-time equivalent circuit Rise-time equivalent circuit The fall-time is faster than the rise time, t f =t r /2 primarily due to different carrier mobilities associated with the p and n- devices: µ n = 2 µ p It is true considering equally sized n and p transistors β n = 2 β p

45 CMOS VLSI Design  If the designer wants to have both n an p transistor with the same rise and fall time: β n / β p = 1  This implies that channel width for the p-device must be increased to approximately two to three times of the n-device: w p = 2 – 3 w n 4: DC and Transient ResponseSlide 45 Trajectory of a n-transistor operating point

46 CMOS VLSI Design4: DC and Transient ResponseSlide 46 Delay Estimation  We would like to be able to easily estimate delay –Not as accurate as simulation –But easier to ask “What if?”  The step response usually looks like a 1 st order RC response with a decaying exponential.  Use RC delay models to estimate delay –C = total capacitance on output node –Use effective resistance R –So that t pd = RC  Characterize transistors by finding their effective R –Depends on average current as gate switches

47 CMOS VLSI Design4: DC and Transient ResponseSlide 47 RC Delay Models  Use equivalent circuits for MOS transistors –Ideal switch + capacitance and ON resistance –Unit nMOS has resistance R, capacitance C –Unit pMOS has resistance 2R, capacitance C  Capacitance proportional to width  Resistance inversely proportional to width Capacitance proportional to width Resistance inversely proportional to width nMOS pMOS

48 CMOS VLSI Design4: DC and Transient ResponseSlide 48  Resistance of a uniform slab: –R =  (l/A) = (  /t) (L/W) where  is the resistivity in ohm-cm, t is the thickness in cm, L is the length, W is the width, and A is the cross-sectional area –Using the concept of sheet resistance, R = R s (L/W) where R s is called the sheet resistance and given in ohms per square Rs =  / t  Gate Capacitance - C g =  ox WL/t ox =  ox A/t ox RC Delay Models

49 CMOS VLSI Design MOS device capacitances  MOS Device capacitances –C gs, C gd = gate-to-channel capacitances, which are lumped at the source and the drain regions. –C sb, C db = source and drain-duiffusion capacitances to bulk (or substrate) –C gb = gate –to-bulk capacitance 4: DC and Transient ResponseSlide 49

50 CMOS VLSI Design4: DC and Transient ResponseSlide 50 1. Off region, where V gs < V t. There is no channel C gs, C gd = 0. 2. Non-saturated region, where V gs - V t. > V ds. C gb = 0 3. Saturated region, where V gs <- V t. < V ds. Channel is heavely inverted. The drain is pinched off causing C gd = 0. MOS device capacitances

51 CMOS VLSI Design RC Delay Models 4: DC and Transient ResponseSlide 51 pMOS capacitance = 2x nMOS capacitance

52 CMOS VLSI Design4: DC and Transient ResponseSlide 52 Example: 3-input NAND  Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

53 CMOS VLSI Design4: DC and Transient ResponseSlide 53 Example: 3-input NAND  Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

54 CMOS VLSI Design4: DC and Transient ResponseSlide 54 Example: 3-input NAND  Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

55 CMOS VLSI Design4: DC and Transient ResponseSlide 55 3-input NAND Caps  Annotate the 3-input NAND gate with gate and diffusion capacitance.

56 CMOS VLSI Design4: DC and Transient ResponseSlide 56 3-input NAND Caps  Annotate the 3-input NAND gate with gate and diffusion capacitance. Resultant capacitance per gate = 2C+3C = 5C Parallel capacitances 3x2C+3C = 9C

57 CMOS VLSI Design4: DC and Transient ResponseSlide 57 3-input NAND Caps  Annotate the 3-input NAND gate with gate and diffusion capacitance.

58 CMOS VLSI Design4: DC and Transient ResponseSlide 58 Elmore Delay  ON transistors look like resistors  Pullup or pulldown network modeled as RC ladder  Elmore delay of RC ladder

59 CMOS VLSI Design4: DC and Transient ResponseSlide 59 Example: 2-input NAND  Estimate worst-case rising and falling delay of 2- input NAND driving h identical gates.

60 CMOS VLSI Design4: DC and Transient ResponseSlide 60 Example: 2-input NAND  Estimate worst-case rising and falling delay of 2- input NAND driving h identical gates.

61 CMOS VLSI Design4: DC and Transient ResponseSlide 61 Example: 2-input NAND  Estimate worst-case rising and falling delay of 2- input NAND driving h identical gates. Parallel capacitances 2C+2C+2C= 6C

62 CMOS VLSI Design4: DC and Transient Response Example: 2-input NAND  Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates.

63 CMOS VLSI Design4: DC and Transient ResponseSlide 63 Example: 2-input NAND  Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates.

64 CMOS VLSI Design4: DC and Transient ResponseSlide 64 Example: 2-input NAND  Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates. Rising time: nMOS - “off” pMOS - “on”

65 CMOS VLSI Design4: DC and Transient ResponseSlide 65 Example: 2-input NAND  Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates.

66 CMOS VLSI Design4: DC and Transient ResponseSlide 66 Example: 2-input NAND  Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates. Consider that the nMOS resistance = (pMOS resistance)/2 = R/2

67 CMOS VLSI Design4: DC and Transient ResponseSlide 67 Example: 2-input NAND  Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates.

68 CMOS VLSI Design4: DC and Transient ResponseSlide 68 Delay Components  Delay has two parts –Parasitic delay 6 or 7 RC Independent of load –Effort delay 4h RC Proportional to load capacitance

69 CMOS VLSI Design4: DC and Transient ResponseSlide 69 Contamination Delay  Best-case (contamination) delay can be substantially less than propagation delay.  Ex: If both inputs fall simultaneously

70 CMOS VLSI Design4: DC and Transient ResponseSlide 70 Diffusion Capacitance  we assumed contacted diffusion on every source/drain  Good layout minimizes diffusion area  Ex: NAND3 layout shares one diffusion contact –Reduces output capacitance by 2C –Merged uncontacted diffusion might help too Capacitance = 2C+2C+3C = 7C

71 CMOS VLSI Design4: DC and Transient ResponseSlide 71 Layout Comparison  Which layout is better?

Download ppt "Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response Greco/Cin-UFPE (Material taken/adapted from Harris’ lecture notes)"

Similar presentations

Design and Implementation of VLSI Systems (EN1600)

Design and Implementation of VLSI Systems (EN1600)
Logic Gate Delay Modeling -1 Bishnu Prasad Das Research Scholar CEDT, IISc, Bangalore

Logic Gate Delay Modeling -1 Bishnu Prasad Das Research Scholar CEDT, IISc, Bangalore
Topics Electrical properties of static combinational gates:

Topics Electrical properties of static combinational gates:
Transistor nMOS Q channel = CV C = C g =  ox WL/t ox = C ox WL V = V gc – V t = (V gs – V ds /2) – V t v =  E  (mobility) E = V ds /L Time for carrier.

Transistor nMOS Q channel = CV C = C g =  ox WL/t ox = C ox WL V = V gc – V t = (V gs – V ds /2) – V t v =  E  (mobility) E = V ds /L Time for carrier.
DC Characteristics of a CMOS Inverter

DC Characteristics of a CMOS Inverter
DC Response DC Response: Vout vs. Vin for a gate Ex: Inverter

DC Response DC Response: Vout vs. Vin for a gate Ex: Inverter
Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response
A Look at Chapter 4: Circuit Characterization and Performance Estimation Knowing the source of delays in CMOS gates and being able to estimate them efficiently.

A Look at Chapter 4: Circuit Characterization and Performance Estimation Knowing the source of delays in CMOS gates and being able to estimate them efficiently.
S. RossEECS 40 Spring 2003 Lecture 21 CMOS INVERTER CMOS means Complementary MOS: NMOS and PMOS working together in a circuit D S V DD (Logic 1) D S V.

S. RossEECS 40 Spring 2003 Lecture 21 CMOS INVERTER CMOS means Complementary MOS: NMOS and PMOS working together in a circuit D S V DD (Logic 1) D S V.
Introduction to CMOS VLSI Design Lecture 3: CMOS Transistor Theory David Harris Harvey Mudd College Spring 2004.

Introduction to CMOS VLSI Design Lecture 3: CMOS Transistor Theory David Harris Harvey Mudd College Spring 2004.
CMOS Transistor and Circuits

CMOS Transistor and Circuits
Introduction to CMOS VLSI Design Lecture 5 CMOS Transistor Theory

Introduction to CMOS VLSI Design Lecture 5 CMOS Transistor Theory
VLSI Design CMOS Transistor Theory. EE 447 VLSI Design 3: CMOS Transistor Theory2 Outline Introduction MOS Capacitor nMOS I-V Characteristics pMOS I-V.

VLSI Design CMOS Transistor Theory. EE 447 VLSI Design 3: CMOS Transistor Theory2 Outline Introduction MOS Capacitor nMOS I-V Characteristics pMOS I-V.
S. RossEECS 40 Spring 2003 Lecture 22 Inside the CMOS inverter, no I D current flows through transistors when input is logic 1 or logic 0, because the.

S. RossEECS 40 Spring 2003 Lecture 22 Inside the CMOS inverter, no I D current flows through transistors when input is logic 1 or logic 0, because the.
1 CMOS Digital System Design MOS Transistor DC Operation.

1 CMOS Digital System Design MOS Transistor DC Operation.
Lecture #26 Gate delays, MOS logic

Lecture #26 Gate delays, MOS logic
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response

Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response
11/5/2004EE 42 fall 2004 lecture 281 Lecture #28 PMOS LAST TIME: NMOS Electrical Model – NMOS physical structure: W and L and d ox, TODAY: PMOS –Physical.

11/5/2004EE 42 fall 2004 lecture 281 Lecture #28 PMOS LAST TIME: NMOS Electrical Model – NMOS physical structure: W and L and d ox, TODAY: PMOS –Physical.
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response Credits: David Harris Harvey Mudd College (Material taken/adapted from Harris’ lecture.

Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response Credits: David Harris Harvey Mudd College (Material taken/adapted from Harris’ lecture.
Lecture #24 Gates to circuits

Lecture #24 Gates to circuits

Similar presentations

Ads by Google