1. 1Presentation Title Revised : N50D00/Rock Lin Instructed : N50D10/Jim C Chen DK1 Power Presentation

2. 2Presentation Title DK1 Block Diagram

3. 3Presentation Title  Please link to >>>>>> Power on sequence block diagram

4. 4Presentation Title 1) Use probe to touch the CN11 pin 2 ( DEBUG_TXD ) without inserting AC adapter. 2) As for oscilloscope, set up Trigger Mode : Normal. 3) Final step that have to insert AC adapter but do not press Power Button. 4) Eventually, we should have 4 set of pulses as below. Procedure Of Checking KBC Pulses

5. 5Presentation Title Good Sign From KBC

6. 6Presentation Title a) If we couldn't have such pulses from KBC. b) Please go back to check the signal step by step. ACAV_IN MAX1999_SHDN# 3D3V_S5 X1( PIN 1, 2, XTAL ) DEBUG_OUT. c) There are several circuit portion listed below. Procedure Of Checking KBC Pulses

7. 7Presentation Title Procedure Of Checking KBC Pulses

8. 8Presentation Title U55 Procedure Of Checking KBC Pulses

9. 9Presentation Title Procedure Of Checking KBC Pulses

10. 10Presentation Title Procedure Of Checking KBC Pulses

11. 11Presentation Title Procedure Of Checking No Power Issues Symptom : 3 LED light turn on entirely (FPC) First Case: a) Firstly, you can jump to check VCC_CORE_S0 power plane. b) Does CPU power comes up? c) If doesn't. Please go back to check with the power sequence from beginning as 5V_S3/+3VSRC SUSPWROK 1D8V_S3/1D5V_S3 RUN_ON_D 1D05V_S0 VCC_CORE_S0. d) These action will check which power plane have no power up. e) The more detailed power sequence waveform have attached from page 12 to page 21.

12. 12Presentation Title Procedure Of Checking No Power Issues Second Case: a) Assumed that CPU voltage can attain 0.9 Volt above. b) We may prove that the rest of power plane before VCC_CORE_S0 power plane would be fine. c) Afterward, please check with ICH_PCIRST# H_CPURST#. ( See fig.1, fig.2 below ) d) If ICH_PCIRST# still can’t exist, we can check the following signal : RESET_OUT#( From KBC) VRM_PWRGD. e) If H_CPURST# can’t driven high, the following action should take is checking the GMCH_PWROK( R431 pin 2 ). f) In addition, we can check whether reference voltage (2/3 VCCP) for GMCH correct or not, that is, GTLREF, H_VREF. ( R38 pin 1, GTLREF ), ( R311 pin 1, H_VREF ).

13. 13Presentation Title Fig.1 ( H_PWRGD, ICH_PCIRST# )

14. 14Presentation Title Fig.2 ( H_CPURST#, ICH_PCIRST# )

15. 15Presentation Title 1) If both H_PWRGD and H_CPURST# driven high as fig.1, fig.2. We’ll keep tracking the next signal which connect between CPU and GMCH, that is, H_ADS#. ( Fig.3 ). 2) We can assume that CPU may failure if we can’t get these pulses in Fig.3. 3) Another case is only show up one pulse in Fig.3 that we can suspect the failure in U40 ( Bios Rom ). Procedure Of Checking No Power Issues

16. 16Presentation Title H_ADS# is the “ first signal ” generated by CPU, Fig.3 ( H_ADS# )

17. 17Presentation Title LPC_LFRAME# WAVEFORM COME OUT AFTER H_ADS# PRODUCED BY CPU ( REFER TO PAGE 20 )

18. 18Presentation Title By the way, If above signal OK. Then we can check the rest of CLK waveforms. 1) Check U62 ( clock GEN ) RN45, RN46 pin 3, 4 CPU CLK ( 100/133 MHz ).

19. 19Presentation Title 2) Check memory CLK ( 200/266 MHz ) which asserts from GMCH. Practically, we can probe the DDR socket ( normal type ) at pin 35, 37.

20. 20Presentation Title N/BS/BBIOSCPU VCC Clock H_CPURST# Reset H_ADS#DMI_RXP/NLPC_LFRAME# H_TRDY# DMI_TXP/N H_D#(63:0) LPC_LAD(3:0) CPU access BIOS data flow

21. 21Presentation Title DK1 POWER SEQUENCE WAVEFORM