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1 COMP541 Final Missing Pieces of MIPS: Adding Memory & I/O Montek Singh Oct 29, 2014
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Memory-Mapped I/O Simple technique for accessing I/O give each I/O device a “fake” memory address give each I/O device a “fake” memory address i.e., CPU reads and writes a specific range of memory locations for I/O devices i.e., CPU reads and writes a specific range of memory locations for I/O devices using lw and sw pretending I/O devices were simply memory locations net effect is reading and writing I/O each device is assigned its own range of memory each device is assigned its own range of memory “address space” example: example: data memory from ’h0000_2000 to ’h0000_3FFF VGA display (screen memory) from ’h0000_4000 to ’h0000_40FF joystick status at ’h0000_6000 mouse status at ’h0000_6004 keyboard status at ’h0000_6008 … etc. 2
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Memory-Mapped I/O Putting data mem at 0x2000 also helps with MARS “Compact, Text at 0” puts data at 0x2000 “Compact, Text at 0” puts data at 0x2000 data mem data mem screen mem screen mem 0x0000 2000 0x0000 3FFF 0000 0000 0000 0000 0010 0000 0000 0000 0000 0000 0000 0000 0011 1111 1111 1111 0x0000 40000000 0000 0000 0000 0100 0000 0000 0000 0x0000 4FFF0000 0000 0000 0000 0100 1111 1111 1111 joystick/kbd 0x0000 6000 0000 0000 0000 0000 0110 0000 0000 0000 gap 0x0000 00000000 0000 0000 0000 (the upper limit will depend on your screen size)
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data mem data mem screen mem screen mem 0x0000 2000 0x0000 3FFF 0000 0000 0000 0000 0010 0000 0000 0000 0000 0000 0000 0000 0011 1111 1111 1111 0x0000 40000000 0000 0000 0000 0100 0000 0000 0000 0x0000 4FFF0000 0000 0000 0000 0100 1111 1111 1111 joystick/kbd 0x0000 6000 0000 0000 0000 0000 0110 0000 0000 0000 gap starting at 0000 0000 0000 0000 Multicycle MIPS (later) Can combine data and instr memories into one MARS assumes this type of unified memory MARS assumes this type of unified memory starting at 0x0000 0000 instr mem instr mem
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The Big Picture CPU, memory and I/O unit, display and joystick data mem data mem screen mem screen mem joystick/kbd pass thru VGA Display Driver memory mapper MIPS Memory and I/O Unit 2 read ports 1 write port 1 read port 1 write port instr mem instr mem
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6 Adding I/O Look at memory-mapped I/O Conceptually like this
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7 In Reality Isolated from CPU On standard buses PCI PCI Ours will typically be simpler Just memory addresses Just memory addresses
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Memory Mapping How to do in Verilog? Let’s do this interactively! Let’s do this interactively! 8
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9 Joystick, mouse, etc. You’ll add joystick or keyboard (or both) into memory locations that you can read e.g., at two locations right above character memory e.g., at two locations right above character memory I will show you next week
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10 How Does Processor Begin? One way is to initialize PC to 0 or some other predefined address or some other predefined address Another possibility is to have a reset each time you hit a reset button, PC starts again at 0 each time you hit a reset button, PC starts again at 0 Make sure to have instructions there Modern computers have flash memory to boot CPU or go to configuration utility Modern computers have flash memory to boot CPU or go to configuration utility On (very) old computers had to enter boot program on front panel On (very) old computers had to enter boot program on front panel
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Summary Add I/O to complete the MIPS processor I/O is “memory-mapped” I/O is “memory-mapped” shares the address space with memory different regions of memory reserved for data mem, display, input devices, etc. Final Project: start thinking about what you want for your demo! start thinking about what you want for your demo! 11
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