1. ECE 331 – Digital System Design Electrical Characteristics of Logic Gates, Circuit Design Considerations, and Programmable Logic Devices

2. Electrical Characteristics of Logic Gates

3. Representing Logic Values Electrical Characteristics

4. ECE 331 - Digital System Design4 Voltage Representing Logic Values Logic 1 Undefined V DD V 1,min V 0,max V SS Logic 0 supply voltage ground

5. ECE 331 - Digital System Design5 Voltage Noise Margin NM H = V OH - V IH NM L = V IL - V OL Undefined V DD V OH V IH V IL V OL V SS supply voltage ground

6. ECE 331 - Digital System Design6 Voltage Levels V IH V IL V IH V IL V OH V OL V OH V OL V OH, V OL, V IH, and V IL are specified in the data sheet for the associated logic gate.

7. ECE 331 - Digital System Design7 Fan-out Electrical Characteristics

8. ECE 331 - Digital System Design8 Fan-out Fan-out is the number of gate inputs that can be properly driven by a single gate output  Current must flow between logic gates  Current is limited by logic gate technology  Current limits fan-out DC Fan-out is the fan-out when the output is at steady-state.  Both high (1) and low (0) output states must be considered when implementing logic circuit design  Select worst-case as limit

9. ECE 331 - Digital System Design9 x f (a) Inverter that drivesn other inverters To inputs of n other inverters N 1 Fan-out Fanout is determined by taking the ratio of the output current (I OH, I OL ) of the driving device to the input current (I IH, I IL ) of the load device(s). The input and output currents are specified in the data sheet of the associated logic gates.

10. ECE 331 - Digital System Design10 Interfacing between Logic Devices Electrical Characteristics

11. ECE 331 - Digital System Design11 Interfacing between Logic Devices Devices in the same logic family have the same electrical characteristics. Devices in different logic families often have different electrical characteristics. In order to interface between logic devices  Must consider the voltage levels of the driving and load devices.  Must consider the current sourced and sunk by the driving and load devices, respectively.

12. ECE 331 - Digital System Design12 Interfacing between Logic Devices Voltage  The V OH of the driving device must be greater than the V IH of the load device.  The V OL of the driving device must be less than the V IL of the load device.  Noise Margin Current  The driving device sources current for one or more load devices.  Must consider the fan-out limit for the driving device.

13. ECE 331 - Digital System Design13 Interfacing between Logic Devices Noise Margin High (NM H ) NM H = V OH – V IH Noise Margin Low (NM L ) NM L = V IL – V OL

14. ECE 331 - Digital System Design14 Example: Determine the high and low noise margins when a 74LS00 NAND gate drives another 74LS00 NAND gate. Electrical Characteristics

15. ECE 331 - Digital System Design15

16. ECE 331 - Digital System Design16 Example: Noise Margin From the 74LS00 data sheet:  V OH_min = 2.7 VV OL_max = 0.4 V  V IH_min = 2.0 VV IL_max = 0.8 V High Noise Margin  NM H = 2.7 V – 2.0 V = 0.7 V Low Noise Margin  NM L = 0.8 V – 0.4 V = 0.4 V

17. ECE 331 - Digital System Design17 Interfacing between Logic Devices Low-state Fanout = Floor[ I OL_max (driver) / I IL_max (load) ] High-state Fanout = Floor[ I OH_max (driver) / I IH_max (load) ] Design the logic circuit based on the minimum of the two fan-out limits.

18. ECE 331 - Digital System Design18 Interfacing between Logic Devices Exceeding fanout limits leads to  Increase in output-low voltage (V OL ) And possibly the wrong logic state  Decrease in output-high voltage (V OH ) And possibly the wrong logic state  Increase in temperature And possible destruction of the circuit / device  Increase in propagation delay

19. ECE 331 - Digital System Design19 forn =1V f forn =4V f V DD Gnd Time0 (c) Propagation times for different values ofn Effect of Fan-out on Propagation Delay

20. ECE 331 - Digital System Design20 Example: Find the fan-out limit of a 74LS00 NAND gate when driving one or more NAND gates on the same chip. Electrical Characteristics

21. ECE 331 - Digital System Design21

22. ECE 331 - Digital System Design22 Example: Fanout Limit From the 74LS00 data sheet:  I OH_max = - 0.4 mAI OL_max = 8.0 mA  I IH_max = 20  AI IL_max = - 0.4 mA Low-state fanout =  Floor[ 8.0 mA / 0.4 mA ] = 20 High-state fanout =  Floor[ 0.4 mA / 20  A ] = 20

23. ECE 331 - Digital System Design23 Example: Determine the noise margins and fanout limit for a 74LS00 NAND gate when driving one or more 74HC00 NAND gates. Electrical Characteristics

24. ECE 331 - Digital System Design24

25. ECE 331 - Digital System Design25 Example: Noise Margin From the 74LS00 data sheet:  V OH_min = 2.7 VV OL_max = 0.4 V From the 74HC00 data sheet:  V IH_min = 3.15 VV IL_max = 1.35 V High Noise Margin  NM H = 2.7 V – 3.15 V = - 0.45 V Low Noise Margin  NM L = 1.35 V – 0.4 V = 0.95 V

26. ECE 331 - Digital System Design26 Example: Fanout Limit From the 74LS00 data sheet:  I OH_max = - 0.4 mAI OL_max = 8.0 mA From the 74HC00 data sheet:  I IH_max = I IL_max = +/- 1  A Low-state fanout =  Floor[ 8.0 mA / 1  A ] = 8000 High-state fanout =  Floor[ 0.4 mA / 1  A ] = 400

27. ECE 331 - Digital System Design27 Programmable Logic Devices

28. ECE 331 - Digital System Design28 Programmable Logic Device Programmable Logic Array (PLA)  Consists of a set of AND gates that feeds a set of OR gates.  Realizes a Boolean expression using the Sum-of-Products (SOP) form. Programmable Array Logic (PAL)  Similar to the PLA  However, only the AND plane is programmable.  The OR plane is fixed.

29. ECE 331 - Digital System Design29 Programmable Logic Array

30. ECE 331 - Digital System Design30 f 1 P 1 P 2 f 2 x 1 x 2 x 3 OR plane AND plane P 3 P 4 Programmable Logic Array

31. ECE 331 - Digital System Design31 f 1 P 1 P 2 f 2 x 1 x 2 x 3 AND plane P 3 P 4 Programmable Array Logic

32. ECE 331 - Digital System Design32 Programmable Logic Devices Complex Programmable Logic Device (CPLD)  Comprises multiple circuit blocks on a single chip, with internal wiring resources to connect the circuit blocks.  Each circuit block is similar to a PLA or PAL. Field Programmable Gate Array (FPGA)  Supports implementation of relatively large logic circuits.  Does not contain AND or OR planes.  Provides logic blocks for the implementation of the required functions.

33. ECE 331 - Digital System Design33 CPLD

34. ECE 331 - Digital System Design34 CPLD

35. ECE 331 - Digital System Design35 FPGA

36. ECE 331 - Digital System Design36 FPGA Logic Block