1. Features of Modern FPGAs
ECE 448
Lecture 16
Features of Modern FPGAs
ECE 448 – FPGA and ASIC Design with VHDL

2. Resources Clive “Max” Maxfield, The Design Warrior’s Guide to FPGAs,
Elsevier, 2004.
ECE 448 – FPGA and ASIC Design with VHDL

3. Resources Xcell Journal available for FREE on line @
FPGA and Structured ASIC Journal
available for FREE by or on the
ECE 448 – FPGA and ASIC Design with VHDL

4. Xilinx FPGA Families Old families XC3000, XC4000, XC5200
Old 0.5µm, 0.35µm and 0.25µm technology. Not recommended for modern designs.
High-performance families
Virtex (220 nm)
Virtex-E, Virtex-EM (180 nm)
Virtex-II (130 nm)
Virtex-II PRO (130 nm)
Virtex-4 (90 nm)
Virtex-5 (65 nm)
Virtex-6 (40 nm) coming in 2009
Low Cost Family
Spartan/XL – derived from XC4000
Spartan-II – derived from Virtex
Spartan-IIE – derived from Virtex-E
Spartan-3 (90 nm)
Spartan-3E (90 nm) – logic optimized
Spartan-3A (90 nm) – I/O optimized
Spartan-3AN (90 nm) – non-volatile,
Spartan-3A DSP (90 nm) – DSP optimized
Spartan-6 (45 nm) – coming in 2009
ECE 448 – FPGA and ASIC Design with VHDL

5. Field Programmable Gate Arrays
ECE 448 – FPGA and ASIC Design with VHDL

6. General structure of an FPGA
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

7. Xilinx CLB ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

8. Simplified view of a Xilinx Logic Cell
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

9. 6-bit LUTs introduced in Virtex 5
4-bit LUTs vs. 6-bit LUTs
6-bit LUTs introduced in Virtex 5
ECE 448 – FPGA and ASIC Design with VHDL

10. RAM Blocks and Multipliers in Xilinx FPGAs
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

11. DSP Blocks
ECE 448 – FPGA and ASIC Design with VHDL

12. Multiplier-Accumulator - MAC
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (

13. Xilinx XtremeDSP
Starting with Virtex 4 family, Xilinx introduced DSP48 block for high-speed DSP on FPGAs
Essentially a multiply-accumulate core with many other features
Now also Spartan-3A and Virtex 5 have DSP blocks

14. DSP48 Slice: Virtex 4

15. DSP48 Functionality
The math portion of the DSP48 slice consists of an 18-bit x 18-bit, two’s complement multiplier followed by three 48-bit datapath multiplexers (with outputs X, Y, and Z) followed by a three-input, 48-bit adder/subtracter.
The data and control inputs to the DSP48 slice feed the arithmetic portions directly or are optionally registered one or two times to assist the construction of different, highly pipelined, DSP application solutions.
The data inputs A and B can be registered once or twice
The other data inputs and the control inputs can be registered once.
Full speed operation is 500 MHz when using the pipeline registers
Equation 1-1 summarizes the combination of X, Y, Z, and CIN by the adder/subtracter.
The CIN, X multiplexer output, and Y multiplexer output are always added together.
This combined result can be selectively added to or subtracted from the Z multiplexer output.
Adder Out = (Z ± (X + Y + CIN)) Equation 1-1
Equation 1-2 describes a typical use where A and B are multiplied, and the result is added to or subtracted from the C register. Selecting the multiplier function consumes both X and Y multiplexer outputs to feed the adder.
The two 36-bit partial products from the multiplier are sign extended to 48 bits before being sent to the adder/subtracter.
Adder Out = C ± (A × B + CIN) Equation 1-2
Figure 1-4 shows the DSP48 slice in a very simplified form. The seven OPMODE bits control the selection of the 48-bit datapaths of the three multiplexers feeding each of the three inputs to the adder/subtracter. In all cases, the 36-bit input data to the multiplexers is sign extended, forming 48-bit input datapaths to the adder/subtracter.
Based on 36-bit operands and a 48-bit accumulator output, the number of “guard bits” (i.e., bits available to guard against overflow) is 12. Therefore, the number of multiply accumulations possible before overflow occurs is Combinations of OPMODE, SUBTRACT, CARRYINSEL, and CIN control the function of the adder/subtracter.
Source: Xilinx

16. Simplified Form of DSP48

17. Mathematical Functions
DSP 48 can perform mathematical functions such as:
Add/Subtract
Accumulate
Multiply
Multiply-Accumulate
Multiplexer
Barrel Shifter
Counter
Divide (multi-cycle)
Square Root (multi-cycle)
Can also create filters such as:
Serial FIR Filter (Xilinx calls this MACC filters)
Parallel FIR Filter
Semi-Parallel FIR Filter
Multi-rate FIR Filters

18. DSP48E Slice : Virtex5

19. Xilinx DSP48

20. Clock Managers
ECE 448 – FPGA and ASIC Design with VHDL

21. A simple clock tree ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

22. Clock Manager ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

23. Jitter ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

24. Removing Jitter ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

25. Frequency Synthesis ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

26. Phase shifting Figure 4-20 ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
Figure 4-20
ECE 448 – FPGA and ASIC Design with VHDL

27. Removing Clock Skew ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

28. Supply Voltage
ECE 448 – FPGA and ASIC Design with VHDL

29. Change in Supply Voltages
Year Technology Core Supply Voltage (V)
ECE 448 – FPGA and ASIC Design with VHDL

30. General-Purpose I/O
ECE 448 – FPGA and ASIC Design with VHDL

31. General-Purpose IO Blocks
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

32. Parallel I/O Standards supported by Virtex 5
LVCMOS (3.3v, 2.5v, 1.8v, 1.5v, and 1.2v)
LVDS, Bus LVDS, Extended LVDS
LCPECL
PCI, PCI-X
HyperTransport (LDT)
HSTL (1.8v, 1.5v, Classes I, II, III, IV)
HSTL_I_12 (unidirectional only)
DIFF_HSTL_I_18, DIFF_HSTL_I_18_DCI
DIFF_HSTL_I, DIFF_HSTL_I_DCI
RSDS_25 (point-to-point)
SSTL (2.5v, 1.8v, Classes I, II)
DIFF_SSTL_I
DIFF_SSTL2_I_DCI
DIFF_SSTL18_I, DIFF_SSTL18_I_DCI
GTL, GTL+
ECE 448 – FPGA and ASIC Design with VHDL

33. Serial I/O Standards supported by Virtex 5
ECE 448 – FPGA and ASIC Design with VHDL

34. Gigabit Transceivers
ECE 448 – FPGA and ASIC Design with VHDL

35. Using High-Speed Tranceivers to Communicate Between Devices
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

36. Using a Bus to Communicate Between Devices
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (

37. Using High-Speed Tranceivers to Communicate Between Devices
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (

38. Effect of Noise on Single Wire and Differential Pair
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (

39. Generating a Differential Pair
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (

40. Multiple Standards for High-Speed Serial Communication
Fibre Channel
InfiniBand
PCI Express (developed by Intel)
RapidIO
SkyRail (developed by MindSpeed Technologies)
10-gigabit Ethernet
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (

41. Using FPGA to Interface Between Multiple Standards
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (

42. An Ideal Signal vs. Signal Seen by Receiver
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (

43. The Effects of Transmitting a Series of Identical Bits
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (

44. Main Elements of the Transceiver Block
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (

45. Ganging Multiple Transceivers Together
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (

46. Pre-emphesis and Equalization
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (

47. Recovering Clock Signal

48. Sampling the Incoming Signal

49. The Effect of Jitter

50. Eye Diagram and Eye Mask
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (

51. Embedded Microprocessors
ECE 448 – FPGA and ASIC Design with VHDL

52. Embedded Microprocessor Cores
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

53. Virtex-II Pro Architecture2 4 6 1 5 3
Features:
Processor Block
RocketIO Multi-Gigabit Transceivers
CLB and Configurable Logic
SelectIO-Ultra
Digital Clock Managers
Multipliers and Block SelectRAM
ECE 448 – FPGA and ASIC Design with VHDL

54. ECE 448 – FPGA and ASIC Design with VHDL

55. Processor Block Contains four components:
Embedded IBM PowerPC 405-D5 RISC CPU core
On-Chip Memory (OCM) controllers and interface
Clock/control interface logic
CPU-FPGA Interfaces
IBM CoreConnect Bus Architecture Features:
Processor Local Bus (PLB)
On-chip Peripheral Bus (OPB)
Device Control Register (DCR) Bus
BRAM
BRAM
Control
OCM Controller
PPC 405
Core
FPGA CLB Array
OCM Controller
Interface Logic
BRAM
BRAM
ECE 448 – FPGA and ASIC Design with VHDL

56. PowerPC Cores ECE 448 – FPGA and ASIC Design with VHDL PowerPC System

57. Embedded Development Kit (EDK)
Hardware Flow
Software Flow
Processor IP,
Microprocessor Peripheral Description Files
VHDL / Verilog
C / C++ Code
Libraries
PlatGen
Synthesizer
Compiler
LibGen
Microprocessor Hardware Specification File
Microprocessor Software Specification File
EDIF IP Netlists
Object Files
ISE / Xflow
System Constraint File
Linker
Bitstream
Data2MEM
Executable
Download to FPGA
ECE 448 – FPGA and ASIC Design with VHDL

58. Configuration of FPGAs
ECE 448 – FPGA and ASIC Design with VHDL

59. Static RAM-based Technology
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

60. SRAM FPGA Configuration
Loading the bitstream into internal memory by delivering it through one of the configuration interfaces
Configuration phases:
Clearing the configuration memory
Initialization
Bitstream loading
Device startup
JTAG
SelectMAP
Slave/Master Serial
ICAP
Correspond to configuration modes
Configuration Device
SRAM FPGA
Bitstream
Configuration
Interface
A series of command and data
Configuration
Logic
Configuration
Memory
ECE 448 – FPGA and ASIC Design with VHDL

61. Configuration of SRAM based FPGAs
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

62. FPGA Configuration Modes
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

63. Serial Load with FPGA as a Master
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

64. Daisy-Chaining FPGAs ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

65. Parallel Load with FPGA as a Master (off-the-shelf memory)
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

66. Parallel Load with FPGA as a Master (special-purpose memory)
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

67. Parallel Load with FPGA as a Slave
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

68. Using the JTEG Port JTEG = Joint Test Action Group, IEEE 1149.1
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

69. Internal Processor Boundary Scan Chain
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

70. Reconfiguration Interfaces in Xilinx FPGAs
Internal Port
ICAP
(Virtex-II)
JTAG
SelectMap (8 bits Parallel)
ECE 448 – FPGA and ASIC Design with VHDL

71. Configuration times of selected FPGA devices
ECE 448 – FPGA and ASIC Design with VHDL