1. Hamming Code, K-maps-Multiplexer Midterm 1 Revision
Lecture 7
Hamming Code, K-maps-Multiplexer Midterm 1 Revision
Prof. Sin-Min Lee
Department of Computer Science

2. Let us play a game ! A volunteer from the audience?
Pick a number, any number, between 1 and 50
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3. Is the Number in Here?
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4. Is the Number in Here?
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5. Is the Number in Here?
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6. Is the Number in Here?
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7. Is the Number in Here?
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8. Is the Number in Here?
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9. And the Number is ….
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11. Richard Hamming
Richard Wesley Hamming, mathematician, pioneer computer scientist, and professor, died of a heart attack on January 7, 1998, in Monterey, California, at the age of 82. His research career began at Bell Laboratories in the 1940s, in the early days of electronic computers, and included the invention of the Hamming error-correcting codes. In the 1970s he shifted to teaching, and at his death he was Distinguished Professor Emeritus of computer science at the Naval Postgraduate School. He is survived by his wife Wanda, a niece, and a nephew.
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13. INFS 515 Digital Logic Level
1948: Error Correction
Error-detecting coding, first developed for telephone switching, is now used throughout the computing and telecommunications industries. In 1948 , R.W. Hamming (left) of Bell Labs developed a general theory for error-correcting schemes in which "check-bits" are interspersed with information bits to form binary words in patterns. When a single error occurs in transmission, the word becomes invalid, but the error is automatically located and corrected.
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16. INFS 515 Digital Logic Level
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17. INFS 515 Digital Logic Level
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18. INFS 515 Digital Logic Level
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28. INFS 515 Digital Logic Level
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29. INFS 515 Digital Logic Level
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30. Truth table to K-Map B A 1 A B P 11 A B P 1
minterms are represented by a 1 in the corresponding location in the K map.
The expression is:
A.B + A.B + A.B
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31. K-Maps Adjacent 1’s can be “paired off”
Any variable which is both a 1 and a zero in this pairing can be eliminated
Pairs may be adjacent horizontally or vertically B A 1
a pair
B is eliminated, leaving A as the term
another pair
A is eliminated, leaving B as the term
The expression becomes A + B
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32. Two Variable K-Map BC A 00 01 11 10 1 A B C P 1 A.B.C + A.B.C + A.B.C1
A.B.C + A.B.C + A.B.C BC A 00 01 11 10 1
One square filled in for each minterm.
Notice the code sequence: – a Gray code.

33. Grouping the Pairs BC A 00 01 11 10 1
equates to B.C as A is eliminated.
Our truth table simplifies to
A.C + B.C as before.
Here, we can “wrap around” and this pair equates to A.C as B is eliminated.
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34. Groups of 4
Groups of 4 in a block can be used to eliminate two variables: BC A 00 01 11 10 1
The solution is B because it is a 1 over the whole block
(vertical pairs) = BC + BC = B(C + C) = B.
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35. Karnaugh Maps Three Variable K-Map
Extreme ends of same row considered adjacent
A BC 00 01 11 10 1 10 00

36. Karnaugh Maps Three Variable K-Map example A BC 00 01 11 10 1 A BC 001
A BC 00 01 11 10 1 1
X = 1 1 1

37. The Block of 4, again
A BC 00 01 11 10 1 1 1 1 1
X = C
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38. Returning to our car example, once more
Two Variable K-Map A B C P 1
A.B.C + A.B.C + A.B.C AB C 00 01 11 10 1
There is more than one way to label the axes of the K-Map, some views lead to groupings which are easier to see.
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39. Karnaugh Maps Four Variable K-Map Four corners adjacent AB CD 00 01 1110 00 01 11 10

40. Karnaugh Maps Four Variable K-Map example AB CD 00 01 11 10 00 01 11

41. Product-of-Sums AB C 00 01 11 10 1 AB C 00 01 11 10 1 A B C P 11
We have populated the maps with 1’s using sum-of-products extracted from the truth table.
We can equally well work with the 0’s AB C 00 01 11 10 1 AB C 00 01 11 10 1
P = (A + B).(A + C)
P = A.B + A.C
equivalent

42. Inverted K Maps
In some cases a better simplification can be obtained if the inverse of the output is considered
i.e. group the zeros instead of the ones
particularly when the number and patterns of zeros is simpler than the ones
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43. Karnaugh Maps Example: Z5 of the Seven Segment Display
X1 X2 X3 X4 Z5 1 2 3 4 5 6 7 8 9
X1X2 X3 X4 00 01 11 10 00 01 11
X1X2 X3 X4 00 01 11 10 10 00 1 1 01 1
Z5 = 11 X X X X X 10 1 X X X
Better to group 1’s or 0’s? X X X X
X1X2 X3 X4 00 01 11 10 00 1 1 01 1 11 X X X X 10 1 X X

44. INFS 515 Digital Logic Level
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45. INFS 515 Digital Logic Level
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46. Karnaugh Map Method of Multiplexer Implementation
Consider the function:
A is taken to be the data variable and B,C to be the select variables.
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47. Example of MUX combo circuit
F(X,Y,Z) = Sm(1,2,6,7)
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48. INFS 515 Digital Logic Level
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49. Implementing the Canonical Sum
The binary decoder generates all minterms of n-variable logic function.
The canonical sum ( sum of minterms ) of a logic functions is obtained by adding all minterms of that function: -Match the order of input bits -Activate Enable inputs
Example :
+5V
74x138 Y0 G1 Y1
G2A Y2
G2B F Y3 Y4 Z A Y5 Y B Y6 X C Y7 49

50. Design Canonical Form w/ MUX
Each input in a MUX is a minterm F A0 A1 A2 A3 S1 S0
8-to-1
Mux S2 A4 A5 A6 A7 1 1 1 1 A B C 50 50

51. Design Canonical Form w/ MUXB F 1 51 51

52. Design Canonical Form w/ MUXEn A B F C 1 A0 C A1 F
4-to-1
Mux A2 1 A3
Vdd S1 S0 A B 52 52

53. Design Canonical Form w/ MUXB C F 1 53 53

54. Design Canonical Form w/ MUXEn B C F 1 A A0 A1 A F
4-to-1
Mux
Vdd A2 A A3 S1 S0 B C 54 54

55. Demultiplexers (DeMux)F A0 A1 A2 A3 S1 S0
4-to-1
Mux D0 D1
1-to-4
DeMux A D2 D3 S1 S0 55 55

56. DeMux Operations 1-to-4 DeMux S1 S0 D3 D2 D1 D0 A 1 D0 D1 A D2 D3 S1A 1 D0 D1
1-to-4
DeMux A D2 D3 S1 S0 56 56

57. DeMux Operations D0 D1 D2 D3 A S1 S0 S1 S0 D3 D2 D1 D0 A 1 57 57

58. Implementing Functions Using Decoders
Example: Full adder
S(x, y, z) = S (1,2,4,7)
C(x, y, z) = S (3,5,6,7)
3-to-8
Decoder 1 2 3 4 5 6 7 S x S2 S1 S0 y C z 58

59. Encoder
Function: given 2n inputs, encode the index of input with 1 as the output. : n
outputs
2n to n
encoder 2n
inputs 59 59

60. Encoders & Priority Encoders
Logic functions
X = I0’I1’I2I3’ + I0’I1’I2’I3
Y = I0’I1I2’I3’ + I0’I1’I2’I3
X = I2I3’ + I3
Y = I1I2’I3’ + I3 X Y I 1 2 3 I I I I X Y 1 2 3 1 x 1 1 x x 1 1 x x x 1 1 1 60 60

61. Binary Adders
For example: add and , ie., = 7110
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62. Half Adder
Truth table
Logic function 62 62

63. Full Adder 63 63

64. Binary Adders Arithmetic Circuit
a combinational circuit for arithmetic operations such as addition, subtraction, multiplication, and division with binary numbers or decimal numbers in a binary code
Addition of 2 binary inputs, 'Half Adder‘
0+0=0, 0+1=1, 1+0=1, 1+1 = 10
S = X'Y + XY' = X Å Y;
C = XY 64

65. Binary Adders Addition of 3 binary inputs, 'Full Adder'
Logic Diagram of Full Adder 65

66. Binary Adders Binary Ripple Carry Adder
sum of two n-bit binary numbers in parallel
4-bit parallel adder
A = 1011, B = 0011 66

67. Binary Adders Carry Lookahead Adder
The ripple carry adder has a long circuit delay
the longest delay: 2 n + 2 gate delay
 Carry Lookahead Adder
reduced delay at the price of complex hardware
a new logic hierarchy
Pi: propagate function
Gi: generate function 67

68. Development of Carry Lookahead Adder
3.8 Binary Adders 68

69. 69