1. ARM HARDWARE DEBUGGER Shane Mahon, Lyndsi Parker, and Drew Shafer

2. Project Objective  To implement a hardware debugger in the FPGA to communicate to the ARM processor through JTAG.  The hardware debugger will be controlled through a serial port to a separate computer running a graphical software interface.

3. Overview  Hardware  JTAG interface to ARM  UART interface to RS232  Bridge from UART to JTAG communication  Software  Serial communication ISA for JTAG commands  Implement debug commands  GUI interface

4. Teamwork Breakdown  Shane Mahon  Physical hardware to connect ARM JTAG pins to FPGA  Simulation of JTAG  Logic analyzer debug  Lyndsi Parker  JTAG interface  JTAG to UART interface  Presentation preparation  Drew Shafer  Software code  Graphical interface  UART code  Simulation of Serial and JTAG

5. Architecture User Interface Software Debug API RS232 UART Hardware Bridge Hardware JTAG Hardware ARM Processor

6. Architecture ARM Processor

8. Architecture ARM to FPGA Connections ARM JTAG FPGA Accessory Pins Logic Analyzer Probes

9. Architecture Hardware sasc_jtag_interfacejtag_topsasc_topsasc_fifo4

10. Architecture JTAG Hardware Reset Wait TLR DR IR RTI Complete

11. Length  Test Logic Reset (resets JTAG state machine on ARM)  Run Test Idle (advances ARM pipeline once)  Instruction Register  Data Register Architecture Bridge Hardware 0000 1111 1000 - - - - 0 - - - - - - - Instruction Variable Length Data

12. Architecture UART Hardware  Downloaded open source UART code  http://www.opencores.org/cores/sasc/ http://www.opencores.org/cores/sasc/  Began debug by creating a loopback  Code required some minor modifications

13. Implementation RS232

14. Implementation JTAG Software  Implemented Functions  Read ID Code  Bypass Register  Halt the Processor  Read/Write a Register  Read/Write Multiple Registers  Read/Write Memory  Execute a Single Instructions  Return from Halt  Code developed from JTAG-Arm9  http://jtag-arm9.sourceforge.net/ http://jtag-arm9.sourceforge.net/

15. Implementation User Interface  Created in Visual Studio using C#

16. Demo: JTAG ID Code

17. Demo: Halting the Processor

18. Demo: Read/Write Registers

19. Demo: Execute Add Instruction

20. Demo: Read/Write Memory

21. Design Tradeoffs  JTAG data register accesses are not pipelined.  Debug instructions are not interleaved.  For simplicity in executing ARM instructions, entire scan chain was shifted although only 33 bits needed for simple instructions.

22. Additional Functionality  Execute code loaded from a file  View disassembly of code  Breakpoints/watch points  Block memory accesses  Standard connector for JTAG to FPGA connections

23. Lessons Learned  Start simulation of Verilog early  Ensure that adequate documentation is available  8 LEDs != Logic Analyzer  Never connect 16.5V directly to the ARM Processor

24. Backup Slides

25. Logic Analyzer Trace  ADDI Instruction

26. Logic Analyzer Trace  Bypass

27. Logic Analyzer Trace  IDCODE

28. Logic Analyzer Trace  Read Debug Status Register

29. Logic Analyzer Trace  Select Scan Chain

30. Logic Analyzer Trace  Write Debug Control Register

31. TLL5000 Connections FPGA BallSchematic NameFunctional Use F26FPGA_ACC4tclk G25FPGA_ACC5tms H25FPGA_ACC6tdi G26FPGA_ACC7tdo H26FPGA_ACC8trst FPGA BallSchematic NameFunctional Use M2RS232_TXtx_o M1RS232_RXrx_i N1RS232_CTScts_i M6RS232_RTSrts_o

32. TLL5000 Connections