1. M.S.P.V.L. Polytechnic College, Pavoorchatram
SYNCHRONOUS COUNTER
M.S.P.V.L. Polytechnic College,
Pavoorchatram

2. Introduction Synchronous counter is a parallel counter.
SYNCHRONOUS – Events that have fixed time relationship with each other and generally, occur at the same time.

3. Synchronous Counter Operation
Digital Circuit’s clock inputs are all wired together.
With all clock inputs wired together, propagation delay is assumed to be equal.
Propagation Delay occurs from the triggering edge of the input clock pulse.
Each FF’s Q-outputs toggle simultaneously.
Response time for a Synchronous counter is faster than Asynchronous circuit.
A 2 Bit Binary Synchronous Counter can be built quite easily.

4. A 2-bit synchronous binary counter

5. Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-flops are assumed to be equal).

6. Synchronous Counter Operation Continued
The timing diagram is similar to an Asynchronous 2Bit Counter.
Using JK FFs, the outputs are toggled based on a positive edge input trigger.

7. Timing diagram for the counter

8. A 3bit Synchronous Binary Counter
This counter uses a “AND” gate to detect Q0 and Q1 outputs of FF0 and FF1.
This condition is unique because both outputs are “Hi” simultaneously.
The “AND” is used to assure that FF2 toggles properly.
The Timing Diagram is similar to a 3 Bit Asynchronous Binary Counter.
The FFs are positive edge triggered devices.
A State Table is another tool used to show the expected outputs of a 4Bit Synchronous Decade Counter.

9. A 3-bit synchronous binary counter
A 3-bit synchronous binary counter. Open file F09-14 to verify the operation.

10. Timing diagram

11. A 4bit Synchronous Binary Counter
This counter uses an “AND” gates to detect Q0, Q1 and Q2 outputs of FF0 and FF1.
This condition is unique because outputs are “Hi” simultaneously.
The “AND” is used to assure that FF2 and FF3 toggles properly.
The Timing Diagram is similar to a 4 Bit Asynchronous Binary Counter.
The FFs are positive edge triggered devices.

12. A 4-bit synchronous binary counter

13. A 4bit Synchronous Decade Counter
This counter uses a “AND” gates and “OR” gates to detect Q0, Q1 and Q2 outputs of FF0, FF1 and FF2 as well as truncating to the appropriate count sequence (MOD 10).
This condition is unique because outputs are “Hi” simultaneously.
The “AND” is used to assure that FF2 and FF3 toggles properly and the “OR” gate for partial decoding the correct truncate count sequence (1001).

14. Continued
The Timing Diagram is similar to a 4 Bit Asynchronous Decade Counter.
The FFs are positive edge triggered devices.
The “AND” and “OR” gates assist in the Partial Decoding for truncating the sequence for MOD 10 counting.
The Timing Diagram is used to show the “Decade” counting sequence of the synchronous counter.

15. A State Table is another tool used to show the expected outputs of a 4Bit Synchronous Decade Counter.
Count value is incremented on the positive edge of the input clock signal.

16. A Synchronous BCD decade counter. Open file F09-17 to verify operation.

17. Timing diagram for the BCD decade counter (Q0 is the LSB).

18. Up/Down 3 Bit Synchronous Counter
An Up/Down 3 Bit Counter is capable of progressing in either direction through a certain sequence.
An Up/Down Counter is also known as “bidirectional counter.”
A 3 Bit Binary counter advances upward in sequence (0,1,2,3,4,5,6,7).
It advances downward in reverse sequence (7,6,5,4,3,2,1,0).
The counter advances to next output state on the positive edge of the input clock.

19. A basic 3-bit up/down synchronous counter
A basic 3-bit up/down synchronous counter. Open file F09-23 to verify operation.

21. The End
….. Thank you……