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ECE 301 – Digital Electronics

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Presentation on theme: "ECE 301 – Digital Electronics"— Presentation transcript:

1 ECE 301 – Digital Electronics
Memory (Lecture #22)

2 Random Access Memory

3 ECE 301 - Digital Electronics
Random Access Memory Static Random Access Memory (SRAM) ECE Digital Electronics

4 ECE 301 - Digital Electronics
Random Access Memory ECE Digital Electronics

5 ECE 301 - Digital Electronics
Random Access Memory Address Decoding ECE Digital Electronics

6 ECE 301 - Digital Electronics
RAM: Address Decoding k-bit address Decoder requires 2k AND gates Each AND gate has k inputs For large k this becomes prohibitive. Use 2-dimensional decoding Two decoders Each decoder requires 2(k/2) AND gates Each AND gate has k/2 inputs Far less combinational logic ECE Digital Electronics

7 ECE 301 - Digital Electronics
RAM: Address Decoding ECE Digital Electronics

8 ECE 301 - Digital Electronics
RAM: Address Decoding The size of a chip package is often dictated by the number of input and output signals. For large memories, the number of address lines often becomes prohibitive. Use address multiplexing The same address lines are used both for the row address and the column address Use time multiplexing to first latch the row address and then latch the column address ECE Digital Electronics

9 ECE 301 - Digital Electronics
RAM: Address Decoding ECE Digital Electronics

10 Building a Bigger Memory System
Random Access Memory Building a Bigger Memory System ECE Digital Electronics

11 ECE 301 - Digital Electronics
RAM Systems Often RAM chips are smaller than the required memory size. What if you need a wider memory? Larger word size What if you need a deeper memory? Greater number of memory locations ECE Digital Electronics

12 Exercise: Design a 32K x 32 memory using RAM chips that are 32K x 8.
RAM Systems Exercise: Design a 32K x 32 memory using RAM chips that are 32K x 8. How many address bits are required? How many data bits are required? ECE Digital Electronics

13 ECE 301 - Digital Electronics
Exercise: 32K x 32 RAM Addr 15 A14 - A0 D31 - D24 8 D23 - D16 D15 - D8 D7 - D0 Data ECE Digital Electronics

14 Exercise: Design a 128K x 8 memory using RAM chips that are 32K x 8.
RAM Systems Exercise: Design a 128K x 8 memory using RAM chips that are 32K x 8. How many address bits are required? How many address bits are connected to the RAM chips? What are the remaining address bits connected to? ECE Digital Electronics

15 ECE 301 - Digital Electronics
Example: 128K x 8 RAM ECE Digital Electronics

16 ECE 301 - Digital Electronics
Read Only Memory ECE Digital Electronics

17 ECE 301 - Digital Electronics
Read Only Memory ROM store “permanent” binary information One-time programmable memory Multiple-time programmable memory Address and Data k address bits n data bits 2k x n ROM includes k-to-2k decoder n 2k-input OR gates ECE Digital Electronics

18 ECE 301 - Digital Electronics
Read Only Memory ECE Digital Electronics

19 ECE 301 - Digital Electronics
Read Only Memory ECE Digital Electronics

20 ECE 301 - Digital Electronics
Read Only Memory ECE Digital Electronics

21 ECE 301 - Digital Electronics
Read Only Memory ECE Digital Electronics

22 ECE 301 - Digital Electronics
Read Only Memory EEPROM (E2PROM) Electrically Erasable Programmable ROM Flash ROM Similar to E2PROM Has additional circuitry to selectively erase and program the memory in-circuit Does not require a special programmer ECE Digital Electronics

23 Programmable Logic Devices
ECE Digital Electronics

24 Programmable Logic Devices
Programmable Logic Arrays (PLA) Programmable Array Logic (PAL) Simple Programmable Logic Device (SPLD) Complex Programmable Logic Device (CPLD) Field Programmable Gate Array (FPGA) ECE Digital Electronics

25 ECE 301 - Digital Electronics
“That's All Folks!” ECE Digital Electronics

26 Acknowledgments The slides used in this lecture were taken, with permission, from those provided by Pearson Prentice Hall for Digital Design (4th Edition). They are the property of and are copyrighted by Pearson Education. ECE Digital Electronics


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