1. EE 447 VLSI Design 4: DC and Transient Response1 VLSI Design DC & Transient Response

2. EE 447 VLSI Design 4: DC and Transient Response2 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation

3. EE 447 VLSI Design 4: DC and Transient Response3 DC Response DC Response: V out vs. V in for a gate Ex: Inverter When V in = 0 -> V out = V DD When V in = V DD -> V out = 0 In between, V out depends on transistor size and current By KCL, must settle such that I dsn = |I dsp | We could solve equations But graphical solution gives more insight

4. EE 447 VLSI Design 4: DC and Transient Response4 Transistor Operation Current depends on region of transistor behavior For what V in and V out are nMOS and pMOS in Cutoff? Linear? Saturation?

5. EE 447 VLSI Design 4: DC and Transient Response5 I-V Characteristics Make pMOS is wider than nMOS such that  n =  p

6. EE 447 VLSI Design 4: DC and Transient Response6 Current vs. V out, V in

7. EE 447 VLSI Design 4: DC and Transient Response7 Load Line Analysis For a given V in : Plot I dsn, I dsp vs. V out V out must be where |currents| are equal in

8. EE 447 VLSI Design 4: DC and Transient Response8 Load Line Analysis V in = 0

9. EE 447 VLSI Design 4: DC and Transient Response9 Load Line Analysis V in = 0.2V DD

10. EE 447 VLSI Design 4: DC and Transient Response10 Load Line Analysis V in = 0.4V DD

11. EE 447 VLSI Design 4: DC and Transient Response11 Load Line Analysis V in = 0.6V DD

12. EE 447 VLSI Design 4: DC and Transient Response12 Load Line Analysis V in = 0.8V DD

13. EE 447 VLSI Design 4: DC and Transient Response13 Load Line Analysis V in = V DD

14. EE 447 VLSI Design 4: DC and Transient Response14 Load Line Summary

15. EE 447 VLSI Design 4: DC and Transient Response15 DC Transfer Curve Transcribe points onto V in vs. V out plot

16. EE 447 VLSI Design 4: DC and Transient Response16 Operating Regions Revisit transistor operating regions RegionnMOSpMOS ACutoffLinear BSaturationLinear CSaturation DLinearSaturation ELinearCutoff

17. EE 447 VLSI Design 4: DC and Transient Response17 Beta Ratio If  p /  n  1, switching point will move from V DD /2 Called skewed gate Other gates: collapse into equivalent inverter

18. EE 447 VLSI Design 4: DC and Transient Response18 Noise Margins How much noise can a gate input see before it does not recognize the input?

19. EE 447 VLSI Design 4: DC and Transient Response19 Logic Levels To maximize noise margins, select logic levels at unity gain point of DC transfer characteristic

20. EE 447 VLSI Design 4: DC and Transient Response20 Transient Response DC analysis tells us V out if V in is constant Transient analysis tells us V out (t) if V in (t) changes Requires solving differential equations Input is usually considered to be a step or ramp From 0 to V DD or vice versa

21. EE 447 VLSI Design 4: DC and Transient Response21 Inverter Step Response Ex: find step response of inverter driving load cap

22. EE 447 VLSI Design 4: DC and Transient Response22 Inverter Step Response Ex: find step response of inverter driving load cap

23. EE 447 VLSI Design 4: DC and Transient Response23 Inverter Step Response Ex: find step response of inverter driving load cap

24. EE 447 VLSI Design 4: DC and Transient Response24 Inverter Step Response Ex: find step response of inverter driving load cap

25. EE 447 VLSI Design 4: DC and Transient Response25 Inverter Step Response Ex: find step response of inverter driving load cap

26. EE 447 VLSI Design 4: DC and Transient Response26 Inverter Step Response Ex: find step response of inverter driving load cap

27. EE 447 VLSI Design 4: DC and Transient Response27 Delay Definitions t pdr : t pdf : t pd : t r : t f : fall time

28. EE 447 VLSI Design 4: DC and Transient Response28 Delay Definitions t pdr : rising propagation delay From input to rising output crossing V DD /2 t pdf : falling propagation delay From input to falling output crossing V DD /2 t pd : average propagation delay t pd = (t pdr + t pdf )/2 t r : rise time From output crossing 0.2 V DD to 0.8 V DD t f : fall time From output crossing 0.8 V DD to 0.2 V DD

29. EE 447 VLSI Design 4: DC and Transient Response29 Delay Definitions t cdr : rising contamination delay From input to rising output crossing V DD /2 t cdf : falling contamination delay From input to falling output crossing V DD /2 t cd : average contamination delay t pd = (t cdr + t cdf )/2

30. EE 447 VLSI Design 4: DC and Transient Response30 Simulated Inverter Delay Solving differential equations by hand is too hard SPICE simulator solves the equations numerically Uses more accurate I-V models too! But simulations take time to write

31. EE 447 VLSI Design 4: DC and Transient Response31 Delay Estimation We would like to be able to easily estimate delay Not as accurate as simulation The step response usually looks like a 1 st order RC response with a decaying exponential. Use RC delay models to estimate delay C = total capacitance on output node Use effective resistance R So that t pd = RC Characterize transistors by finding their effective R Depends on average current as gate switches

32. EE 447 VLSI Design 4: DC and Transient Response32 RC Delay Models Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nMOS has resistance R, capacitance C Unit pMOS has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width

33. EE 447 VLSI Design 4: DC and Transient Response33 Example: 3-input NAND A 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

34. EE 447 VLSI Design 4: DC and Transient Response34 3-input NAND Caps Annotate the 3-input NAND gate with gate and diffusion capacitance.

35. EE 447 VLSI Design 4: DC and Transient Response35 3-input NAND Caps Annotate the 3-input NAND gate with gate and diffusion capacitance.

36. EE 447 VLSI Design 4: DC and Transient Response36 Elmore Delay ON transistors look like resistors Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder

37. EE 447 VLSI Design 4: DC and Transient Response37 Example: 2-input NAND Estimate worst-case rising and falling delay of 2-input NAND driving h identical gates.

38. EE 447 VLSI Design 4: DC and Transient Response38 Example: 2-input NAND Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates.

39. EE 447 VLSI Design 4: DC and Transient Response39 Example: 2-input NAND Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates.

40. EE 447 VLSI Design 4: DC and Transient Response40 Example: 2-input NAND Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates.

41. EE 447 VLSI Design 4: DC and Transient Response41 Example: 2-input NAND Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates.

42. EE 447 VLSI Design 4: DC and Transient Response42 Example: 2-input NAND Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates.

43. EE 447 VLSI Design 4: DC and Transient Response43 Example: 2-input NAND Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates.

44. EE 447 VLSI Design 4: DC and Transient Response44 Delay Components Delay has two parts Parasitic delay 6 or 7 RC Independent of load Effort delay 4h RC Proportional to load capacitance

45. EE 447 VLSI Design 4: DC and Transient Response45 Contamination Delay Best-case (contamination) delay can be substantially less than propagation delay. Ex: If both inputs fall simultaneously

46. EE 447 VLSI Design 4: DC and Transient Response46 Diffusion Capacitance we assumed contacted diffusion on every s / d. Good layout minimizes diffusion area Ex: NAND3 layout shares one diffusion contact Reduces output capacitance by 2C Merged uncontacted diffusion might help too

47. EE 447 VLSI Design 4: DC and Transient Response47 Layout Comparison Which layout is better?