1. Introduction to CMOS VLSI Design Lecture 2: Standard Cell Design Layout
Salman Zaffar
IqraUniversity,
Spring 2012
Slides from D. Harris, Harvey Mudd College USA

2. Gate Layout Layout can be very time consuming
Design gates to fit together nicely
Build a library of standard cells
Standard cell design methodology
VDD and GND should abut (standard height)
Adjacent gates should satisfy design rules
nMOS at bottom and pMOS at top
All gates include well and substrate contacts
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3. Example: Inverter
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4. Example: NAND3 Horizontal N-diffusion and p-diffusion strips
Vertical polysilicon gates
Metal1 VDD rail at top
Metal1 GND rail at bottom
32 l by 40 l
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5. Stick Diagrams Stick diagrams help plan layout quickly
Need not be to scale
Draw with color pencils or dry-erase markers
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6. Wiring Tracks A wiring track is the space required for a wire
4 l width, 4 l spacing from neighbor = 8 l pitch
Transistors also consume one wiring track
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7. Well spacing Wells must surround transistors by 6 l
Implies 12 l between opposite transistor flavors
Leaves room for one wire track
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8. Area Estimation Estimate area by counting wiring tracks
Multiply by 8 to express in l
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9. Example: O3AI Sketch a stick diagram for O3AI and estimate area
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10. Example: O3AI Sketch a stick diagram for O3AI and estimate area
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11. Example: O3AI Sketch a stick diagram for O3AI and estimate area
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12. Standard Cells Uniform cell height Uniform well height
M1 VDD and GND rails
M2 Access to I/Os
Well / substrate taps
Exploits regularity
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13. Layout through Synthesis
Synthesize HDL into gate-level netlist
Place & Route using standard cell library
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