1. Curtis Mayberry Texas Instruments HPA Linear Applications 8/19/11
PLC Front-end
Curtis Mayberry
Texas Instruments
HPA Linear Applications
8/19/11

2. Background Student at Iowa State University Originally from Ames, IA
Interest in Analog applications and design
Graduating December 2011

3. Coop Term Goals Complete PLC Front-end reference design including:
Schematic
Layout
Testing
Documentation
Continue developing analog circuit analysis skills
Create a board-level analog circuit design
Learn about applications engineering and its role in TI’s business
Learn about TI as an employer

4. Programmable Logic Controller
Programmable automation controller
Used in a variety of industries including the automotive, chemical, and food industries
Microcontroller offers reprogrammable real-time
control solution
4 major Components:
Power supply
Controller
Communications
Input/Output
Universal voltage Input: 0-5v, ±5v, 0-10v, ±10v
Current loop sensor communication: 0-20mA, 4-20mA
Temperature sensors: thermistor, RTD, thermocouple
Pressure, flow, level, vibration and motion sensors
Digital I/O (GPIO)
Analog Output (DAC8760)

5. Motivation #1 collateral request from FAEs
Existing ADI reference design
Customer Requests and New Customer Opportunities

6. Project Definition PLC Analog Front-End Focus on analog Inputs:
Universal voltage Input: 0-5v, ±5v, 0-10v, ±10v
Current loop sensor communication: 0-20mA, 4-20mA
Temperature sensors: thermistor, RTD, thermocouple
SM-USB-Dig controller
Labview Interface to SM-USB-Dig
Documentation
Create design review and final presentation
Ensure a smooth transition to next stage of project

7. Block Diagram Stage 1 Stage 2 RTD TC Thermistor +/-10v, +/-5v 4-20mA
Signal
Conditioning
ADC
Microcontroller
High-Accuracy
Stage 1 Only
DAC
Super-Mini Dig
Labview

8. Implementation

9. Schematic Schematic design review
Minor schematic design revisions made following review

10. Layout Optimized Analog inputs Recessed power and control circuitry
Short, symmetric traces
Recessed power and control circuitry

11. Board Assembly and Troubleshooting
No Errors in Analog Front-end
Assembled V and I Front-end for early software development
Minor Errors contained in power and Control circuitry
Five known errors:
Pull up resistors on LDO EN pins
Move pull up on digital switch (trace needed to be cut)
Ground connection needed to SM-USB-DIG
Need to move SM-USB-DIG connector closer to edge of board
Need pull-up resistors on CS lines

12. Software Started with SM-Dig shell
Added CS control to select front-end
Added DMM Control
Added Data logging
Added Data Displays for 6 front-ends
Added configuration capabilities
for all 6 front-end modules
Labview Interface Front Panel
Labview Interface DMM Control

13. Testing: Temperature Sensing

14. Testing: Temperature Sensing
All Temperature Sensors were submerged and read between 0 oC and 125oC
Thermal bath wasn’t settling at negative temperatures
Post-processed 3 point calibration

15. Thermistor Input (Direct)
Uncalibrated Worst Case Error: 0.4 oc
3 point Calibration (35oc, 65oc, 105oc)
Calibrated Worst Case Error: 0.3 oc
0.24% accuracy

16. Thermistor B Input (Bridge)
Uncalibrated Worst Case Error: 0.9 oc
3 point Calibration (35oc, 65oc, 105oc)
Calibrated Worst Case Error: 0.38 oc
0.304% Accuracy

17. RTD Input Outlier Removed at 15oC
Uncalibrated Worst Case Error: 0.9 oc
3 point Calibration (35oc, 65oc, 105oc)
Calibrated Worst Case Error: oc
0.012%

18. Thermocouple Uncalibrated Worst Case Error: 1.2 oc
3 point Calibration (35oc, 65oc, 105oc)
Calibrated Worst Case Error: 0.4 oc
0.32% error
Thermistor may have saturated at low temp

19. Results: Temperature Sensing
Maximum calibrated Error 0oC – 125oC
Thermistor: 0.3oC
Thermistor B: 0.38oC
RTD: oC
Thermocouple: 0.4oC
Error Summary
Calibrated
Uncalibrated
Mag (oC)
Percent
Thermistor
0.3
0.24%
0.4
0.32%
Thermistor B
0.38
0.30%
0.9
0.72%
RTD
0.015
0.01%
Thermocouple
1.2
0.96%

20. Testing: Universal Inputs

21. Testing: Universal Inputs
Post-processed 3 point calibration
Tested using a Fluke precision voltage and current source in 0.5 V or 0.5 mA step size
Input measured using HP 8.5 digit digital multimeter

22. Universal Voltage: ±10v Outlier Removed at 5.5 V
Uncalibrated Worst Case Error: 10 mV
0.05% Accuracy
3 point Calibration (-6v, 0v, 6v)
Calibrated Worst Case Error: mV
% Accuracy

23. Universal Voltage: 0 - 10v Outlier Removed at 5.5 V
Uncalibrated Worst Case Error: 10 mV
0.1% Accuracy
3 point Calibration (2v, 5v, 8v)
Calibrated Worst Case Error: 0.35 mv
% Accuracy
Worse than +/-10v

24. Universal Voltage: ±5v Outlier Removed at -0.5 V
Uncalibrated Worst Case Error: 3 mV
0.03% Accuracy
3 point Calibration (-3v, 0v, 3v)
Calibrated Worst Case Error: 0.25 mV
0.0025%

25. Universal Voltage: 0 - 5v Uncalibrated Worst Case Error: 2.5 mV
0.05% Accuracy
3 point Calibration (0.5v, 2.5v, 4.5v)
Calibrated Worst Case Error: 0.15 mV
0.003% Accuracy

26. Current Loop: 4-20 mA Uncalibrated Worst Case Error: 1.8 uA
0.0115%
3 point Calibration (6.5mA, 12mA, 17.5mA)
Outlier removed at 14mA
Calibrated Worst Case Error: 2.5 uA
0.0156%
Calibration ineffective due to no consistent gain or offset error, main error component is current source
Change in Error when the source changed output range

27. Current Loop: 0-20 mA Uncalibrated Worst Case Error: 22uA
0.11% Accuracy
3 point Calibration (3.5mA, 10mA, 16.5mA)
Calibrated Worst Case Error: 21 uA
0.105% Accuracy
0 point due to offset limitations of circuiy

28. Results: Universal Front-Ends
Calibrated maximum error:
Universal V
±10 v: mV
0-10 v: 0.35 mV
±5 v: 0.25 mV
0-5 v: 0.15 mV
Current Loop
4-20 mA: 2.5 uA
0-20 mA: 21 uA
Error Summary
Calibrated
Uncalibrated
Mag
Percent
±10v
0.153mV
765u%
10mV
0.05%
0-10v
0.35mV
1.75m%
0.10%
±5v
0.25mV
2.5m%
3mV
0.03%
0-5v
0.15mV
3m%
2.5mV
Table & %

29. Accomplishments Completed PLC Front-End Design Completed Forum Post
PLC Research
Sensor Research
Component Selection
Schematic Design and Review
Layout Design and Review
Fabrication
Software
Debugging
Testing
Completed Forum Post
Learned a lot about board-level development, Op-amps, and about TI’s business

30. Other Accomplishments
Volunteered:
Day of Hope
Disability Connection Carnival
Networked with teammates and other coops
Learned about analog applications
Learned about the relationship between field and factory applications engineering
Developed a better understanding of all the engineering roles

31. Project Continuation and Career Plans
Final Goal: Complete PLC Reference Design utilizing TI parts
Progress will continue during second stage
Potential Microcontroller TI 32-bit Stellaris LM3S1Z16
Potential output DAC: DAC8760
Career Plans:
Attend graduate school for analog design
Return to TI for another Coop Experience as a graduate student

32. Feedback Great Project Excellent Mentoring by Pete and Collin
Interesting and rewarding
Well-defined and complete
Excellent Mentoring by Pete and Collin
Given Freedom to work independently while still having support available
Great job with on-boarding and providing the resources I needed
Great teachers for both Technical and non-technical material
AFA conference and Tucson Testing Trip were Great Opportunities
CORT relocation service hard to work with before coming to TI
Evaluate Experience

33. Thank You Collin Wells Pete Semig Art Kay Matt Hann
Special Thank You to my mentors:
Collin Wells
Pete Semig
Also to my managers:
Art Kay
Matt Hann
Data Converter Applications Team
Tom Hendrick, Greg Hupp, Kevin Duke, Tony Calabria

34. Appendices Appendix A: Elaborated Testing Results
Appendix B: Design review

35. Appendix A: Elaborated Testing Results
Calibration Curves, raw data plots, resistance plots

36. Thermistor

37. Thermistor B

38. RTD Input with Outlier Removed

39. RTD Input with Outlier at 15oc

40. Thermocouple

41. Universal Voltage: ±10v – no outlier

42. Universal Voltage: ±10v – with Outlier

43. Universal Voltage: 0 - 10v – no Outlier

44. Universal Voltage: 0 - 10v –with Outlier

45. Universal Voltage: ±5v – no Outlier

46. Universal Voltage: ±5v - with Outlier

47. Universal Voltage: 0 - 5v

48. Current Loop: 4-20 mA - no Outlier

49. Current Loop: 4-20 mA with Outlier

50. Current Loop: 0-20 mA - no Outlier

51. Appendix B: Design Review
Original Design Review
7-5-11

52. Revised Project Description

53. Block Diagram Stage 1 Stage 2 RTD TC Thermistor +/-10v, +/-5v 4-20mA
Cost-Effective
Signal
Conditioning
ADC
Microcontroller
High-Accuracy
Super-Mini Dig
Labview

54. The Plan
May 16: First Day
May 21: Project Definition & training (1 week)
June 5 - June 10: FAE conference in Tucson (1 week)
July 5: Block Diagrams, calculations (accuracy), simulations, Part selection & ordering, initial schematic (4 weeks)
July 14: PCB layout (2 weeks)
July 21: Basic LabView Coding & Testing preparation (1 week)
July 29: Initial lab results -Oven(~1 weeks)
August 3: Accuracy tests (Tucson?)
August 5: Final Report (2 days)
August 10: Preliminary Presentation (2 days)
August 12: Final Presentation (2 days)
August 18: Last Day (1 week)

55. 0-10v and +/- 10v, 0-5v and +/- 5v, 4-20mA
Universal Inputs
0-10v and +/- 10v, 0-5v and +/- 5v, 4-20mA

56. Universal Voltage Input
0-5v, 0-10v, +/- 5v and +/- 10v universal voltage input
Change resistance values to change input voltage levels
Second order RC filter with poles at 39 Hz and 3900Hz
Opamp to scale down input
2.5v reference generated to scale input
Opa2333: Low offset voltage and drift, rail-to-rail input, dual opamp part

59. Noise Calculations: Voltage Reference
2.5v Reference
REF5025: 625nVRMS
OPA333: 869 nVRMS
Filter KTC noise: 202.8nVRMS
Reference Output 10kΩ: nVRMS
Total Noise: 1.108µVRMS
Current Noise: 26.34nVRMS (negligible)

60. Noise Calculations Total Noise: 1.2µVRMS Input Filter
82nF filter KTC noise: 224 nVRMS
820pF filter noise: nVRMS
Total Noise: nVRMS
Amplifier Noise:
Feedback Network (16.67kΩ): 828nVRMS
OPA333 noise: 869.5nVRMS
Total Noise: 1.2µVRMS

61. Noise Calculations: Total
ADC V+ input noise total: 1.503µVRMS
ADC V- input noise total:1.089uVRMS

62. Noise Calculations: Bringing it all together
ADC noise: 1.35 µVRMS
Noise at Apga =1 and 5 SPS

63. Resistor Mismatch Errors (Worse Case)
Resistor Options (worse case)
Set 1: µV (0.1% resistors)
Set 2: mV (0.1% resistors)
Set 2: mV (0.05% resistors)
Set 2:666.8 µV (0.02% resistors)
Total: 1.797mV
Set 1
Set 2

64. Resistor Tolerance Monte Carlo Simulation
Ran Monte Carlo Simulation using 0.1% resistors
2.5 mV max error on output
Used an ideal op-amp to isolate the error source
Small variation between resistor tolerances

65. Error Estimation ADC Level shifting OPA2333 2.5v Reference OPA2333
15µV offset
INL: 6 ppm
Gain Error: 0.02%
External Reference: 0.05%*2.024V = mV
Total: mV
Level shifting OPA2333
Offset: 10 µV
Offset drift: 0.05 µV/oc
CMRR >106 dB
PSRR: 5 µV/V (max)
2.5v Reference OPA2333
Offset drift: 0.05 µV/oc (3µV over 25oC ± 60oC temperature range)

66. Error Estimation Resistor Mismatch: 1.797 mV
REF v reference: 1.25 mV offset is cancelled out
Total:
with no “interference”: mV

67. Simulation: +/- 10v

68. Simulation: +/- 5v

70. Universal Current input
4-20mA
Second order RC filter
Internal 2.048v reference
221Ω shunt converts 4-20mA to 884mV-4.420V
OPA2333: Rail-to-Rail common mode input, low offset voltage and drift

72. Simulation

73. 2.5v reference

74. Differential output

75. Noise Analysis Total noise: 11.729 µVPP
OPA333 buffer noise: nVRMS
Resistor Noise
10kΩ: nV
16kΩ: 123 nV
1.6kΩ: 31.1 nV
V+ Total Noise: nVRMS
V- Total Noise: µVRMS (Same as Vinput V-)
ADC noise: 1.35 µVRMS
Noise at Apga =1 and 5 SPS
Total noise: µVPP

76. Error Estimation ADC Shunt resistor tolerance: 20mA*221*.1% =4.42 mV
15µV offset
INL: 6 ppm
gain error: 0.02%
Noise error: 7.78 µVpp
External Reference: mV
Shunt resistor tolerance: 20mA*221*.1% =4.42 mV
Level shifting OPA333
Offset: 10 µV
Offset drift: 0.05 µV/oc
CMRR >106 dB
PSRR: 5 µV/V (min)
2.5v Reference OPA333
Offset drift: 0.05 µV/oc (3µV over 25oC ± 60oC temperature range)
CMRR >130 dB
PSRR: 2 µV/V
REF5025: 1.25mV
Total

78. Targeted industrial temperature range: -40oc to 85oc
Temperature Sensors
Thermistor
RTD
Thermocouple
Targeted industrial temperature range: -40oc to 85oc

79. Thermistor Temperature proportional to resistance
Calibrated: 25oC and 85oC
NTC thermistor
30kΩ 25oC
2 Designs:
Single-ended
Bridged

81. Simulation

82. Error Estimation Resistor Mismatch: 374.81µV Current Accuracy:0v
Ratio metric measurement
Thermistor Errors: mV
Thermistor 25oC R-tolerance: 3.731mV (R±1%)
Beta Error: 3.37 mV (Beta±1%)
ADC Errors:
15µV offset
INL: 6 ppm
gain error: 0.02%
External reference R: 2mV
Minimum 4.4 mV/oC
Total Error: 5.425mV (~1.23oC)

85. Simulation

86. Error Estimation Resistor Mismatch: 1.677mV (0.1% resistors)
Current Accuracy: 0v
Ratio metric reading (external ref)
Mismatch between current sources:
±0.15% of FS (50 µV) = 75nV (negligible)
Thermistor Errors: mV
Thermistor 25oC R-tolerance: 3.731mV (R±1%)
Beta Error: 3.37 mV (Beta±1%)
ADC Errors: 400.5µV
15µV offset
INL: 6 ppm
gain error: 0.02%
Minimum 4.4 mV/oC
Total Error: mV

88. RTD PT100, PT 1000 Resistance proportional to temperature
Callendar-Van Dusen equation

90. Simulation

91. Error Estimation Class A RTD probe: ±0.15oC @ 0oC ADC Errors: 400.5µV
15µV offset
INL: 6 ppm
gain error: 0.02%
External reference tolerance:
Total Error: mV

93. Thermocouple Seebeck effect Need to measure voltage across the element
Cold junction compensation: RTD close to the cold junction
PCB layout designed to keep the cold junction isothermal with the RTD
Types: K, J, T, E, N, R, S, B
Different materials, temperature ranges, TC
Example: K type: ~55µV/oC

95. Error Estimation RTD Error: 2.040 mV
Thermocouple element error: Varies by type
Max element error (using K type): 1.1oC or 0.4%

97. Digital Interface
SM-USB-DIG

99. Stage 2 Interface Add MCU Excluded from stage 1 (Rev. A)
MCU controls data converters
MCU communicates through SM-USB- DIG to computer
Adds extra capabilities

100. Power
Powered by a lab supply for prototyping
Banana plug input jack

101. Floor plan
Front-Ends
Control
and Power

102. The Plan
May 16: First Day
May 21: Project Definition & training (1 week)
June 5 - June 10: FAE conference in Tucson (1 week)
July 5: Block Diagrams, calculations (accuracy), simulations, Part selection & ordering, initial schematic (4 weeks)
July 14: PCB layout (2 weeks)
July 21: Basic LabView Coding & Testing preparation (1 week)
July 29: Initial lab results -Oven(~1 weeks)
August 3: Accuracy tests (Tucson?)
August 5: Final Report (2 days)
August 10: Preliminary Presentation (2 days)
August 12: Final Presentation (2 days)
August 18: Last Day (1 week)