Presentation is loading. Please wait.

Presentation is loading. Please wait.

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 7 Microsequencer Control Unit Design.

Published byLaura Summers Modified over 9 years ago

Similar presentations

Presentation on theme: "Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 7 Microsequencer Control Unit Design."— Presentation transcript:

1 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 7 Microsequencer Control Unit Design

2 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter Outline Basic Microsequencer DesignBasic Microsequencer Design Very Simple MicrosequencerVery Simple Microsequencer Relatively Simple MicrosequencerRelatively Simple Microsequencer Reducing the Number of MicroinstructionsReducing the Number of Microinstructions Microcoded vs. Hardwired ControlMicrocoded vs. Hardwired Control Pentium MicroprocessorPentium Microprocessor

3 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Micro-stuff Micro-operationsMicro-operations MicroinstructionsMicroinstructions MicroprogramsMicroprograms

4 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Generic Microsequencer

5 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Generating the Next Address Current Address + 1Current Address + 1 Address specified by microinstructionAddress specified by microinstruction Microsubroutine registerMicrosubroutine register Mapping hardwareMapping hardware

6 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Microinstruction Format

7 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Types of Microcode HorizontalHorizontal VerticalVertical DirectDirect

8 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 A Very Simple Microsequencer

9 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Mapping Logic

10 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 State Addresses StateAddress FETCH1 0000 (0) FETCH2 0001 (1) FETCH3 0010 (2) ADD1 1000 (8) ADD2 1001 (9) AND1 1010 (10) AND2 1011 (11) JMP1 1100 (12) INC1 1110 (14)

11 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Partial Microcode StateAddressSELADDR FETCH1 0000 (0) 00001 FETCH2 0001 (1) 00010 FETCH3 0010 (2) 1XXXX ADD1 1000 (8) 01001 ADD2 1001 (9) 00000 AND1 1010 (10) 01011 AND2 1011 (11) 00000 JMP1 1100 (12) 00000 INC1 1110 (14) 00000

12 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Micro-operations MnemonicMicro-Operation ARPC AR  PC ARDR AR  DR[5..0] PCIN PC  PC + 1 PCDR PC  DR[5..0] DRM DR  M IRDR IR  DR[7..6] PLUS AC  AC + DR AND AC  AC^DR ACIN AC  AC + 1

13 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Preliminary Horizontal Microcode

14 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Optimized Horizontal Microcode

15 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Signals

16 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Generic Vertical Microcode Decoding

17 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Field Assignments Simultaneous micro-operations in different fieldsSimultaneous micro-operations in different fields

18 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Field Assignments Simultaneous micro-operations in different fieldsSimultaneous micro-operations in different fields Include a NOP in each fieldInclude a NOP in each field

19 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Field Assignments Simultaneous micro-operations in different fieldsSimultaneous micro-operations in different fields Include a NOP in each fieldInclude a NOP in each field Distribute remaining micro-operations to minimize total number of bits requiredDistribute remaining micro-operations to minimize total number of bits required

20 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Field Assignments Simultaneous micro-operations in different fieldsSimultaneous micro-operations in different fields Include a NOP in each fieldInclude a NOP in each field Distribute remaining micro-operations to minimize total number of bits requiredDistribute remaining micro-operations to minimize total number of bits required Group together micro-operations that modify the same registerGroup together micro-operations that modify the same register

21 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Micro-operation Assignments M1M2 NOPNOP DRMPCIN

22 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Micro-operation Assignments M1M2 NOPNOP DRMPCIN ACINPCDR PLUSARPC ANDAIDR

23 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Micro-operation Assignments M1M2 NOPNOP DRMPCIN ACINPCDR PLUSARPC ANDAIDR

24 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Micro-operation Assignments and Field Values

25 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Vertical Microcode

26 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Micro-operation Generation

27 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Nanoinstructions

28 Directly Generating Control Signals Output control signals instead of micro- operationsOutput control signals instead of micro- operations No external decoding requiredNo external decoding required No external hardware required to generate control signalsNo external hardware required to generate control signals More difficult to codeMore difficult to code

29 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Preliminary Direct Microcode

30 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Optimize Direct Microcode

31 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Relatively Simple Microsequencer No changes toNo changes to –Instruction set –Data paths –ALU

32 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Modified State Diagram

33 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Microsequencer Hardware

34 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 State Assignments

35 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Condition Values

36 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Branch Types

37 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Branch Logic

38 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Partial Microcode

39 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Partial Microcode (continued)

40 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Micro-operations

41 Horizontal Microcode

42 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Horizontal Microcode

43 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Horizontal Microcode

44 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Signals

45 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Reducing the Number of Microinstructions MicrosubroutinesMicrosubroutines Microcode JumpsMicrocode Jumps

46 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Microsubroutines

47 Revised State Assignments

48 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Microsequencer with Microsubroutines

49 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Revised Branch Types

50 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Revised Branch Logic

51 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Revised Microcode

52 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Microcode Jumps

53 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Revised Microcode

54 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Microprogrammed Control vs. Hardwired Control Complexity of the instruction setComplexity of the instruction set

55 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Microprogrammed Control vs. Hardwired Control Complexity of the instruction setComplexity of the instruction set Ease of modificationEase of modification

56 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Microprogrammed Control vs. Hardwired Control Complexity of the instruction setComplexity of the instruction set Ease of modificationEase of modification Clock speedClock speed

57 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 The Pentium Microprocessor

58 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Summary Basic Microsequencer DesignBasic Microsequencer Design Very Simple MicrosequencerVery Simple Microsequencer Relatively Simple MicrosequencerRelatively Simple Microsequencer Reducing the Number of MicroinstructionsReducing the Number of Microinstructions Microcoded vs. Hardwired ControlMicrocoded vs. Hardwired Control Pentium MicroprocessorPentium Microprocessor

Download ppt "Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 7 Microsequencer Control Unit Design."

Similar presentations

Control Unit Implemntation

Control Unit Implemntation
CHAPTER 16 MICROPROGRAMMED CONTROL DR. H. WATSON FRANCISCO VASQUEZ

CHAPTER 16 MICROPROGRAMMED CONTROL DR. H. WATSON FRANCISCO VASQUEZ
CS1104: Computer Organisation School of Computing National University of Singapore.

CS1104: Computer Organisation School of Computing National University of Singapore.
Chapter 7: Microprogrammed Control

Chapter 7: Microprogrammed Control
PART 5: (2/2) Processor Internals CHAPTER 15: CONTROL UNIT OPERATION 1.

PART 5: (2/2) Processor Internals CHAPTER 15: CONTROL UNIT OPERATION 1.
1 ITCS 3181 Logic and Computer Systems 2014 B. Wilkinson Slides8.ppt Modification date: Nov 3, 2014 Random Logic Approach The approach described so far.

1 ITCS 3181 Logic and Computer Systems 2014 B. Wilkinson Slides8.ppt Modification date: Nov 3, 2014 Random Logic Approach The approach described so far.
UNIT-III CONTROL UNIT DESIGN

UNIT-III CONTROL UNIT DESIGN
Chapter 16 Control Unit Operation No HW problems on this chapter. It is important to understand this material on the architecture of computer control units,

Chapter 16 Control Unit Operation No HW problems on this chapter. It is important to understand this material on the architecture of computer control units,
CS364 CH17 Micro-programmed Control

CS364 CH17 Micro-programmed Control
Chapter 16 Control Unit Implemntation. A Basic Computer Model.

Chapter 16 Control Unit Implemntation. A Basic Computer Model.
Chapter 15 IA 64 Architecture Review Predication Predication Registers Speculation Control Data Software Pipelining Prolog, Kernel, & Epilog phases Automatic.

Chapter 15 IA 64 Architecture Review Predication Predication Registers Speculation Control Data Software Pipelining Prolog, Kernel, & Epilog phases Automatic.
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 6 CPU Design.

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 6 CPU Design.
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 5 Register Transfer Languages.

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 5 Register Transfer Languages.
S. Barua – CPSC 440 CHAPTER 5 THE PROCESSOR: DATAPATH AND CONTROL Goals – Understand how the various.

S. Barua – CPSC 440 CHAPTER 5 THE PROCESSOR: DATAPATH AND CONTROL Goals – Understand how the various.
Computer Organization and Architecture

Computer Organization and Architecture
Micro-operations Are the functional, or atomic, operations of a processor. A single micro-operation generally involves a transfer between registers, transfer.

Micro-operations Are the functional, or atomic, operations of a processor. A single micro-operation generally involves a transfer between registers, transfer.
Lecture 8 Presented By Dr. Shazzad Hosain Asst. Prof. EECS, NSU.

Lecture 8 Presented By Dr. Shazzad Hosain Asst. Prof. EECS, NSU.
Lecture 16 Today’s topics: –MARIE Instruction Decoding and Control –Hardwired control –Micro-programmed control 1.

Lecture 16 Today’s topics: –MARIE Instruction Decoding and Control –Hardwired control –Micro-programmed control 1.
Introduction to Computer Organization and Architecture Micro Program ภาษาเครื่อง ไมโครโปรแกรม.

Introduction to Computer Organization and Architecture Micro Program ภาษาเครื่อง ไมโครโปรแกรม.
CPU Design. Introduction – The CPU must perform three main tasks: Communication with memory – Fetching Instructions – Fetching and storing data Interpretation.

CPU Design. Introduction – The CPU must perform three main tasks: Communication with memory – Fetching Instructions – Fetching and storing data Interpretation.

Similar presentations

Ads by Google