1. Digital System Design Verilog ® HDL Useful Modeling Techniques Maziar Goudarzi

2. 2005Verilog HDL2 Today Program Procedural Continuous Assignment Overriding Parameters Conditional Compilation and Execution Useful System Tasks

3. Procedural Continuous Assignment Useful Modeling Techniques

4. 2005Verilog HDL4 Procedural Continuous Assignment Overrides, for a certain time, the effect of regular assignments to a variable. Two types  assign/deassign Works only on register data types  force/release Works on both register and net data types Note:  Not synthesizable. Use only for modeling and simulation

5. 2005Verilog HDL5 Procedural Continuous Assignment (cont’d) assign/deassign  Keywords assign : overrides regular procedural assignments LHS: reg or concatenation of regs. No nets. No arrays. No bit-select or part-select deassign : re-enables regular procedural assignments  After deassign : Last value remains on the register until a new procedural assignment changes it.

6. 2005Verilog HDL6

7. 2005Verilog HDL7 Procedural Continuous Assignment (cont’d) force/release  Keywords: force : overrides all procedural/continuous/ procedural continuous assignments release : re-enables other assignments Hence, assignments in priority order: 1. force 2. assign (procedural continuous) 3. Procedural/continuous assignments

8. 2005Verilog HDL8 force/release on reg variables

9. 2005Verilog HDL9 force/release on nets Net value immediately returns to its normal assign ed value when released

10. Overriding Parameters Useful Modeling Techniques

11. 2005Verilog HDL11 Overriding Parameters Two methods  defparam statement  Module instance parameter value assignment defparam statement  Keyword: defparam  Syntax: defparam = ;

12. 2005Verilog HDL12

13. 2005Verilog HDL13 Overriding Parameters (cont’d) Module instance parameter values  Parameters are overridden when the module is instantiated  Syntax: #( ) ;

14. 2005Verilog HDL14 Example with multiple parameters

15. Conditional Compilation and Execution Useful Modeling Techniques

16. 2005Verilog HDL16 Conditional Compilation Usage:  To compile some part of code under certain conditions Keywords:  ‘ifdef, `else, `endif  ‘define to define the flag

17. 2005Verilog HDL17

18. 2005Verilog HDL18 Conditional Execution Usage:  To execute some part of code when a flag is set at runtime  Used only in behavioral modeling Keywords:  $test$plusargs Syntax:  $test$plusargs( )

19. 2005Verilog HDL19

20. Useful System Tasks Useful Modeling Techniques

21. 2005Verilog HDL21 Useful System Tasks File Output Opening a file  Syntax: = $fopen( “ ” );  is a 32 bit value, called multi-channel descriptor  Only 1 bit is set in each descriptor  Standard output has a descriptor of 1 (Channel 0)

22. 2005Verilog HDL22 Useful System Tasks File Output (cont’d) Writing to files  $fdisplay, $fmonitor, $fstrobe  $strobe, $fstrobe The same as $display, $fdisplay, but executed after all other statements schedule in the same simulation time  Syntax: $fdisplay(, p1, p2,…, pn); Closing files $fclose( );

23. 2005Verilog HDL23 Example: Simultaneously writing to multiple files

24. 2005Verilog HDL24 Useful System Tasks Random Number Generation Syntax: $random; $random( ); Returns a 32 bit random value

25. 2005Verilog HDL25 Useful System Tasks Initializing Memory from File Keywords:  $readmemb, $readmemh Used to initialize memory ( reg [3:0] mem[0:1023] ) Syntax: $readmemb(“ ”, ); $readmemb(“ ”,, ); $readmemb(“ ”,,, ); The same syntax for $readmemh

26. 2005Verilog HDL26

27. 2005Verilog HDL27 Useful System Tasks Value Change Dump (VCD) File ASCII file containing information on  Simulation time  Scope and signal definitions  Signal value changes Keywords  $dumpvars  $dumpfile  $dumpon  $dumpoff  $dumpall

28. 2005Verilog HDL28

29. 2005Verilog HDL29 Today Summary Introduced a number of modeling techniques useful in various applications

30. 2005Verilog HDL30 Other Notes Homework 8  Chapter 9: All exercises with ModelSim, except for 3 and 5 3 and 5 in paper and pencil Due date: Sunday, Day 11th