1. EE/CS 120A Lab 4
LAB 3 report due on
this Friday 2:00pm

2. Last week Part1 (optional) Lab 3 BCD to 7 Segment LED display BCD
Control which one will be turned on
Implement on FPGA

3. This week Flight Attendant Call System (demo & simulation)
Rising-edge Detector (demo & simulation)
Lab 4
LED Display Time-Multiplexing Circuit (simulation)
Lab 4 report due on Next Friday 2:00pm
2/13/2015 2:00pm

4. Check out connecting wires
Room: Palve

5. Flight Attendant Call System
3 inputs: Call, Cancel and CLK
1 output: LED

6. Caution Function generator (rightmost) Square waveform
Output voltage CANNOT greater than 3.3V
Set between 3-3.3V
Otherwise, it will burn your FPGA!!

7. Flight Attendant Call System
Lab manual:
Truth table (transition table)
schematic
Equations
UCF file
simulation (for Question part)

8. Rising-edge Detector 2 inputs: signal input and CLK 1 output: LED
If the CLK is slow enough, why we only can use switch, instead of button?

9. Rising-edge Detector Hint: At least 3 states Double think
Design by yourself:
State diagram
truth table(transition table)
Equations
Schematic
simulation
UCF
Demo
Hint: At least 3 states
Double think
Don’t go to

10. LED Display Time-Multiplexing Circuit
How to display different number on each 7 segment LED?
Answer: time multiplexing
NOTICE!!
Here “0” means on
“1”means off
For more information, read lab1 manual

11. LED Display Time-Multiplexing Circuit
HEX_TO_LEDSEG (lab manual)
Mux (ISE)
Decoder (ISE)
Wire splitter (slides)
Clock_counter_4state (by yourself)

12. LED Display Time-Multiplexing Circuit
VHDL code on lab manual

13. LED Display Time-Multiplexing Circuit
MUX
Can be found on “symbol”by
typing “M4_1E”
Rename it as Mux(7:0) to make
It can receive bus data

14. LED Display Time-Multiplexing Circuit
Decoder
Can be found on “symbol”by
typing “D2_4E”

15. LED Display Time-Multiplexing Circuit
Wire_spliter
Design by yourself
See next slides

16. How to create a wire spliter

17. LED Display Time-Multiplexing Circuit
Clock_counter_4state
Design by yourself

18. Further reading
On ilearn
Important
Read it before part 3

19. Common mistake Remember create different project for each part !!
Set right FPGA parameters when create new project
Remember create different project for
each part !!

20. Lab manual
Circuit &
UCF
Loading bit file
Show me

21. THANKS
Research Lab
WCH 234