1. ECE 331 – Digital System Design Sequential Circuit Design (Lecture #23) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and were used with permission from Cengage Learning.

2. Fall 2010ECE 331 - Digital System Design2 Material to be covered … Chapter 16: Sections 1 – 5

3. Fall 2010ECE 331 - Digital System Design3 Sequential Circuit Design Understand specifications Draw state graph (to describe state machine behavior) Construct state table (from state graph) Perform state minimization (if necessary) Encode states (aka. state assignment) Create state-assigned table Select type of Flip-Flop to use Determine Flip-Flop input equations and FSM output equation(s) Draw logic diagram

4. Fall 2010ECE 331 - Digital System Design4 Sequential Circuit Design 1.Given the problem statement, determine the required relationship between the input and output sequences and derive a state table. For many problems it is easiest to first construct a state graph. 2.Reduce the table to a minimum number of states. First, eliminate duplicate rows by row matching and, then, form an implication table and follow the procedure in Section 15.3. 3.If the reduced table has m states (2 n – 1 < m ≤ 2 n ), n flip-flops are required. Assign a unique combination of flip-flop states to correspond to each state in the reduced table. The guidelines given in Section 15.8 may prove helpful in finding an assignment which leads to an economical circuit.

5. Fall 2010ECE 331 - Digital System Design5 Sequential Circuit Design 1.Form the transition table by substituting the assigned flip-flop states for each state in the reduced state table. The resulting transition table specifies the next states of the flip-flops and the output in terms of the present states of the flip-flops and the input. 2.Plot next-state maps and input maps for each flip-flop and derive the flip-flop input equations. (Depending on the type of gates to be used, either determine the sum-of-products form from the 1’s on the map or the product-of-sums form from the 0’s on the map.) Derive the output functions. 3.Realize the flip-flop input equations and the output equations using the available logic gates. 4.Check your design by signal tracing, computer simulation, or laboratory testing.

6. Fall 2010ECE 331 - Digital System Design6 Examples

7. Fall 2010ECE 331 - Digital System Design7 Design a sequential logic circuit to realize the following state table: Example #1: FSM Design P.S.N.S.Z X = 0X = 1 aic1 bbi1 ccg1 dic0 ede0 fic0 gef0 hha1 iac1

8. Fall 2010ECE 331 - Digital System Design8 Design in progress … Example #1: FSM Design

9. Fall 2010ECE 331 - Digital System Design9 Example #1: FSM Design My solution using D Flip-Flops:

10. Fall 2010ECE 331 - Digital System Design10

11. Fall 2010ECE 331 - Digital System Design11

12. Fall 2010ECE 331 - Digital System Design12

13. Fall 2010ECE 331 - Digital System Design13

14. 14 The author's solution using D Flip-Flops: Example #1: FSM Design State assignment

15. Fall 2010ECE 331 - Digital System Design15 Example #1: FSM Design My solution using JK Flip-Flops:

16. Fall 2010ECE 331 - Digital System Design16

17. Fall 2010ECE 331 - Digital System Design17

18. Fall 2010ECE 331 - Digital System Design18

19. 19 The author's solution using JK Flip-Flops: Example #1: FSM Design

20. Fall 2010ECE 331 - Digital System Design20 Future site of a second example. Example #2: FSM Design

21. Fall 2010ECE 331 - Digital System Design21 Questions?