1. ITCS 3181 Logic and Computer Systems 2014 B. Wilkinson Slides6.ppt Modification date: Oct 30, 2014 1 Processor Design Specifying the Actions Internal Architecture of a Simple Processor

2. 2 (Not representative of modern computer, later on that)

3. 3 MDR and MAR registers Added to hold data or from memory and address to select memory location:

4. 4 Internal Operation Operation of processor divided into two phases: Fetch cycle Next instruction is fetched from memory Execute cycle Fetched instruction is executed These cycles are repeated as each instruction is executed.

5. 5 Fetch Cycle Select instruction:

6. 6 Fetch instruction:

7. 7 Register Transfer Notation Mostly, actions within processor can be described by the transfer of the contents of one location to another location (registers or units). Use a register transfer language (RTL) notation. Example To transfer the contents of register MDR to register IR, we write: IR  MDR

8. 8 May add time of action: T 2 : IR  MDR The transfer is to take place at time period T 2.

9. 9 Fetch Cycle Fetch cycle actually breaks down into several steps: T 0 :MAR  PCSelect next instruction T 1 :MDR  [MAR]Memory read operation, get instr. from memory T 2 :IR  MDRLoad instruction into instruction register T 3 :PC  PC + 4Increment program counter in preparation for next fetch cycle Could be done simultaneously

10. 10 Fetch Cycle Fetch cycle with last two steps done simultaneously: T 0 :MAR  PCSelect next instruction T 1 :MDR  [MAR]Mem. read op., get instr. from mem. T 2 :IR  MDR; PC  PC + 4 Load instruction into instr. register Increment prog. counter in prep. for next fetch cycle

11. 11 Execute Cycle Breaks down into several steps depending upon instruction fetched. In our design, execution cycle steps start at T 3. To be able to specify certain steps, need to know machine instruction format. We will give representative formats, which will be used in subsequent designs later.

12. 12 Source and destination registers We will use the notation: Rs1for the first source register Rs2for the second source register Rdfor the destination register for register-register instructions as specified in the instruction. Some instructions may only have one source register and/or no destination register.

13. 13 Temporary registers In some designs, it may be necessary to introduce temporary registers to hold Rs1, Rs2, Rd, say called A, B, and C. Then: A  Rs1Contents of first source register copied to A B  Rs2Contents of second source register copied to B will occur automatically whether or not they required by the instruction. If not required, A and B are not accessed subsequently. Similarly if C is loaded, the operation: Rd  CCopy C to destination register occurs automatically.

14. 14 Execute Cycle for Add Instruction Register-register addressing Example: ADD Rd, Rs1, Rs2 T 3 :Rd  Rs1 + Rs2Perform addition and pass result back to Rd

15. 15 Execute Cycle for Add Instruction Immediate Addressing ADDI Rd, Rs1, 123 T 3 :Rd  Rs1 + IR 15-0 Perform addition and pass result back to Rd IR 15-0 means here bits 15 to 0 of IR register Assumes bits 15 to 0 in IR holds the constant (123 above)

16. 16 Other Arithmetic/Logic Instructions Other arithmetic and logic instructions have similar sequences of steps. Simply replace the add operation in: T 3 :Rd  Rs1 + Rs2Perform addition and pass result back to Rd or T 3 :Rd  Rs1 + IR 15-0 Perform addition and pass result back to Rd with the appropriate arithmetic or logic operation.

17. 17 Execute Cycle for Memory Reference Instructions Load Instruction LD Rd, 100[Rs1] where 100 is a constant in the instruction (IR 15-0 ) T 3 :MAR  Rs1 + IR 15-0 Compute memory address T 4 :MDR  [MAR]Memory read operation T 5 :Rd  MDRGet memory contents, load into Rd LD

18. 18 Store Instruction ST 100[Rs1], Rs2 where 100 is a constant in the instruction (IR 15-0 ) T 3 :MAR  Rs1 + IR 15-0 Compute memory address T 4 :MDR  Rs2Get contents of register T 5 :[MAR]  MDRMemory write operation

19. 19 Branch Instructions Bcond Rs1, L1 where cond specifies the condition, E, NE, L, G, GE, or LE. T 3 : Rs1 - 0Compare Rs1 with zero T 4 : if (condition TRUE) PC  PC + IR 15-0 Load PC with target address Offset stored in instruction may need to be offset – 4 since PC already incremented by 4 by this time. Also need to take into account the offset is a word offset - not shown here.

20. 20 Jump Instruction PC-Relative Addressing J L1 T 3 :PC  PC + IR 25-0 Load PC with target address Again offset stored in instruction may need to be offset - 4

21. 21 Jump Instruction Register-Indirect Addressing J 100[Rs1] where the offset (100 above) is held in IR 15-0 T 3 :PC  Rs1 + IR 15-0 Compute effective address and load PC with final target address

22. 22 Jump and Link Instruction JAL L1 T 3 :R31  PCStore return address in R31 T 4 :PC  PC + IR 25-0 Goto L1

23. 23 CALL/RET Instructions Even though our design does not have CALL and RET instructions, let us just list the steps for these instructions: CALL proc1 T 3 :SP  SP – 4Decrement stack pointer (by 4 if 32-bit addresses) T 4 :MAR  SP T 5 :MDR  PCPC holds return address T 6 :[MAR]  MDRCopy PC onto stack (return address) T 7 :PC  IR 25-0 Goto to procedure (address of proc1 held in IR 25-0 ) RET T 3 :MAR  SP T 4 :MDR  [MAR]Get return address from stack T 5 :PC  MDRReturn T 6 :SP  SP + 4Increment stack pointer (by 4 if 32-bit addresses)

24. 24 State Diagram for Processor

25. 25 Register-Register Instructions The arithmetic and logic instructions operating upon pairs of registers - Could be many such instructions. For simplicity, let us assume the following six operations: ADDAddition SUBSubtract MULTMultiply DIVDivide ANDLogical AND ORLogical OR

26. 26 State diagram for register-register instructions All very similar form: MUL/DIV almost certain to require more that one cycle but this is ignored here.

27. 27 Register-Constant Instructions The arithmetic and logic instructions operating upon one register and an immediate constant For simplicity, let us assume the following six operations: ADDIAddition SUBISubtract ANDILogical AND ORILogical OR SHLLogical shift left (number of places given by constant) SLRLogical shift right (number of places given by constant) The “I” is used here to indicate immediate addressing.

28. 28 State diagram for register-constant instructions All very similar form:

29. 29 State Diagram with Load and Store instructions

30. 30 Conditional Branch Instructions Let us assume the conditional branch instruction of the format: Bcond, Rs1, L1 (not using a CCR) and the following four operations: BLBranch if Rs1 less than zero BGBranch if Rs1 greater than zero BEBranch if Rs1 equal zero BNEBranch if Rs1 not equal zero Question – is that sufficient?

31. 31 Execute Cycle for Branch Instruction In this case we need to select on of two sets of actions: If branch condition true = do actions (alter PC) If branch condition false, generally do nothing.

32. 32 State Diagram of Branch Instructions All of similar format:

33. 33 State Diagram of Jump Instructions

34. 34 Could combine states 22, 24, 26, and 28 into one state, and combine states 29 and 32 into one state. However in our design will only combine 29 and 32 to get 32 states in total (0 to 31):

35. 35 Questions Next step is to implement state diagrams.