1. Lecture 12b: Adders

2. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 17: Adders 2 Generate / Propagate  Equations often factored into G and P  Generate and propagate for groups spanning i:j  Base case  Sum:

3. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 17: Adders 3 PG Logic

4. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 17: Adders 4 Carry-Ripple Revisited

5. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 17: Adders 5 Carry-Ripple PG Diagram

6. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 17: Adders 6 Carry-Skip Adder  Carry-ripple is slow through all N stages  Carry-skip allows carry to skip over groups of n bits –Decision based on n-bit propagate signal

7. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 17: Adders 7 Carry-Skip Adder  Carry-ripple is slow through all N stages  Carry-skip allows carry to skip over groups of n bits –Decision based on n-bit propagate signal

8. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 17: Adders 8 Carry-Lookahead Adder  Carry-lookahead adder computes G i:0 for many bits in parallel.  Uses higher-valency cells with more than two inputs.

9. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 17: Adders 9 Carry-Lookahead Adder  Carry-lookahead adder computes G i:0 for many bits in parallel.  Uses higher-valency cells with more than two inputs.

10. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 17: Adders 10 Tree Adder  If lookahead is good, lookahead across lookahead! –Recursive lookahead gives O(log N) delay  Many variations on tree adders

11. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 17: Adders 11 PG Diagram Notation

12. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 17: Adders 12 Sklansky

13. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 17: Adders 13 Brent-Kung

14. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 17: Adders 14 Kogge-Stone

15. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 17: Adders 15 Han-Carlson

16. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 17: Adders 16 Knowles [2, 1, 1, 1]

17. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 17: Adders 17 Ladner-Fischer

18. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 17: Adders 18 Taxonomy Revisited

19. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 17: Adders 19 Summary ArchitectureClassificationLogic Levels Max Fanout TracksCells Carry-RippleN-111N Carry-Skip n=4N/4 + 5211.25N Carry-Inc. n=4N/4 + 2412N Brent-Kung(L-1, 0, 0)2log 2 N – 1212N Sklansky(0, L-1, 0)log 2 NN/2 + 110.5 Nlog 2 N Kogge-Stone(0, 0, L-1)log 2 N2N/2Nlog 2 N Adder architectures offer area / power / delay tradeoffs. Choose the best one for your application.