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Galen SasakiEE 260 University of Hawaii1 Building D Flip Flops Combinational Circuit Components –Switches –Voltage inverters D Clocked Latch –Feedback.

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Presentation on theme: "Galen SasakiEE 260 University of Hawaii1 Building D Flip Flops Combinational Circuit Components –Switches –Voltage inverters D Clocked Latch –Feedback."— Presentation transcript:

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2 Galen SasakiEE 260 University of Hawaii1 Building D Flip Flops Combinational Circuit Components –Switches –Voltage inverters D Clocked Latch –Feedback to store bits D Flip Flop –Two D clocked latches

3 Galen SasakiEE 260 University of Hawaii2 Building D Flip Flops Primitive Combinational Circuits (Switches/Transisters) D Clocked Latches D Flip Flops

4 Galen SasakiEE 260 University of Hawaii3 Combinational Circuit Components Normally Open Switch L open H closed Normally Closed Switch H open L closed Control = LControl = H

5 Galen SasakiEE 260 University of Hawaii4 Combinational Circuit Components Voltage Inverters (2 symbols) Active Device LH LH

6 Galen SasakiEE 260 University of Hawaii5 A Simple 1-Bit Memory QD State value (1 bit) Input to load new state value

7 Galen SasakiEE 260 University of Hawaii6 A Simple 1-Bit Memory QD Two configurations: Hold (store)= hold onto the state value Load = load a new state value State value (1 bit) Input to load new state value

8 Galen SasakiEE 260 University of Hawaii7 Holding (Storing) With Voltage Inverters Devices drive each other

9 Galen SasakiEE 260 University of Hawaii8 Holding (Storing) With Voltage Inverters Devices drive each other H

10 Galen SasakiEE 260 University of Hawaii9 Holding (Storing) With Voltage Inverters Devices drive each other H L H

11 Galen SasakiEE 260 University of Hawaii10 Holding (Storing) With Voltage Inverters Devices drive each other H LL H

12 Galen SasakiEE 260 University of Hawaii11 Holding (Storing) With Voltage Inverters Devices drive each other H LL H L HH L

13 Galen SasakiEE 260 University of Hawaii12 Simple Memory: Two Configurations QD Two configurations: Hold (store)= hold onto the state value Load = load a new state value State value (1 bit) Input to load new state value

14 Galen SasakiEE 260 University of Hawaii13 Simple Memory: Two Configurations DQDQ HoldLoad

15 Galen SasakiEE 260 University of Hawaii14 Simple Memory: Two Configurations DQDQ HoldLoad Switches

16 Galen SasakiEE 260 University of Hawaii15 D Clocked Latch Q clock D clock = L : Hold clock = H : Load

17 Galen SasakiEE 260 University of Hawaii16 D Clocked Latch DQ Clock It similar to a D flip flop but it reacts to the clock differently Q Clock DQ Clock = H = L Hold Q = D It’s “transparent” Load

18 Galen SasakiEE 260 University of Hawaii17 Comparing Flip Flop and Latch D Q Clock D Q-FlipFlop Q-Latch

19 Galen SasakiEE 260 University of Hawaii18 Comparing Flip Flop and Latch D Q Clock D Q-FlipFlop Q-Latch T1T2 T3

20 Galen SasakiEE 260 University of Hawaii19 Comparing Flip Flop and Latch D Q Clock D Q-FlipFlop Q-Latch

21 Galen SasakiEE 260 University of Hawaii20 Comparing Flip Flop and Latch D Q Clock D Q-FlipFlop Q-Latch Store

22 Galen SasakiEE 260 University of Hawaii21 D Flip Flop vs. D Clocked Latch D flip flop –Triggered on positive edge of clock –Output Q (and state) changes only at a time instant D clocked latch –Output Q changes (with D) while clock is H –Output Q changes during a window of time –Trickier to use since lots of changes can happen during a time duration Flip flops are preferred to latches in designing circuits Latches are used in memory circuits, e.g., RAM

23 Galen SasakiEE 260 University of Hawaii22 D Flip Flop DQ Clock DQ

24 Galen SasakiEE 260 University of Hawaii23 D Flip Flop DQ Clock DQ Clock = L Load D Q Hold

25 Galen SasakiEE 260 University of Hawaii24 D Flip Flop DQ Clock DQ Clock = L Load D Q Hold Clock = HHold Load D Q

26 Galen SasakiEE 260 University of Hawaii25 D Flip Flop Clock DQ DQ Hold (output doesn’t change) Load (loads input) Input really doesn’t get stored until the upward clock transition L

27 Galen SasakiEE 260 University of Hawaii26 D Flip Flop Clock DQ DQ Hold (output doesn’t change) Load (loads input) Input really doesn’t get stored until the upward clock transition HH L

28 Galen SasakiEE 260 University of Hawaii27 D Flip Flop DQ Clock D Q DQ DQ Hold (output doesn’t change) Load (loads input) Input really doesn’t get stored until the upward clock transition Hold Load (transfers state to output) HH L H H

29 Galen SasakiEE 260 University of Hawaii28 Summary Combinational circuit components –switches and voltage inverters D clocked latch –Built from switches and voltage inverters –2 configurations: load and hold D flip flop –Built from two D latches in series

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