1. Lecture 8 Shelving in Superscalar Processors (Part 1)
Advanced Computer Architecture
Lecture 8 Shelving in Superscalar Processors (Part 1)
Give qualifications of instructors:
DAP
teaching computer architecture at Berkeley since 1977
Co-athor of textbook used in class
Best known for being one of pioneers of RISC
currently author of article on future of microprocessors in SciAm Sept 1995 RY
took 152 as student, TAed 152,instructor in 152
undergrad and grad work at Berkeley
joined NextGen to design fact 80x86 microprocessors
one of architects of UltraSPARC fastest SPARC mper shipping this Fall

2. Direct Issue

3. The principle of shelving: Indirect Issue

4. Design Space of Shelving

5. Scope of Shelving

6. Layout of Shelving Buffers

7. Implementation of Shelving Buffer

8. Basic Variants of Shelving Buffers

9. Using a Combined Buffer for Shelving, Renaming, and Reordering

10. Number of Shelving Buffer Entries

11. Number of read and write ports
how many instructions may be written into (input ports) or
read out from (output parts) a particular shelving buffer in a cycle
depend on individual, group, or central reservation stations

12. Shelving: Operand Fetch Policy

13. Operand Fetch Policies

14. Operand fetch during instruction issue
Reg. file

15. Operand fetch during instruction dispatch
Reg. file