1. EE42/100 Fall 2005 Prof. Fearing 1 Week 12/ Lecture 21 Nov. 15, 2005 1.Overview of Digital Systems 2.CMOS Inverter 3.CMOS Gates 4.Digital Logic 5.Combinational Blocks 6.Latches and Flip Flops 7.Registers and Counters Reading: Hambley 12.7, 7

2. EE42/100 Fall 2005 Prof. Fearing 2 1. Digital System Overview I/O module

3. EE42/100 Fall 2005 Prof. Fearing 3 1.1 IO Module CPU A/D SensorsActuators amplifier/filter amplifier/switch D/A serial/parallel conversion communications

4. EE42/100 Fall 2005 Prof. Fearing 4 Digital to Analog/Analog to Digital +-+- +5 A>BA DAC B Counter (comparator)

5. EE42/100 Fall 2005 Prof. Fearing 5 Digital Circuits – Introduction Digital word: –Each binary digit is called a bit –A series of bits form a word Byte is a word consisting of 8-bits Advantages of digital signal –Digital signal is more resilient to noise  can more easily differentiate high (1) and low (0), e.g. 3.3V represents ``1’’, 0.0 V represents ``0’’ –easier to store/recover, transmit/receive CPU A/D SensorsActuators amplifier/switch D/A amplifier/filter Digital Analog signal x(t), real value x, real value t signal x(n), binary value x, (x = 0 or 1) integer value n faster processing for simple filters low level signals high power signals example: b=[b2:b0] = b2 2 2 + b1 2 1 + b0 2 0 [101 2 ] = 4+1 = 5 [1000.01 2 ] = 8 + 0.25 = 8.25 10 b2 b1 b0

6. EE42/100 Fall 2005 Prof. Fearing 6 Digital Building Blocks Combinational y=f(x) gates (and, or, not, …) multiplexer adder decoder Sequential q n+1 =f(x,q n ) flip-flop register shift register counter

7. EE42/100 Fall 2005 Prof. Fearing 7 The CMOS Inverter: Intuitive Perspective V DD RnRn V IN = V DD CIRCUIT SWITCH MODELS V DD RpRp V IN = 0 V V OUT V OL = 0 VV OH = V DD Low static power consumption, since one MOSFET is always off in steady state V DD V IN V OUT S D G G S D

8. EE42/100 Fall 2005 Prof. Fearing 8 N-Channel MOSFETP-Channel MOSFET V GS S semiconductor oxide G V DS IDID +  +  D

9. EE42/100 Fall 2005 Prof. Fearing 9 CMOS Inverter Voltage Transfer Characteristic V IN V OUT V DD 0 0 N: off P: lin N: lin P: off N: lin P: sat N: sat P: lin N: sat P: sat A BDE C

10. EE42/100 Fall 2005 Prof. Fearing 10 CMOS Inverter Load-Line Analysis V OUT =V DSn I Dn =-I Dp 0 – V GSp =V IN -V DD + V IN = V DD + V GSp increasing V IN increasing V IN V IN = 0 V V IN = V DD V DD V OUT = V DD + V DSp V DSp = 0 V DSp = - V DD – V DSp =V OUT -V DD + 0

11. EE42/100 Fall 2005 Prof. Fearing 11 Power Dissipation due to Direct-Path Current V DD -V T VTVT time v IN : i:i: I peak V DD 0 0 i S D G G S D V DD v OUT v IN Energy consumed per switching period: t sc

12. EE42/100 Fall 2005 Prof. Fearing 12 ABF 00 01 10 11 A F B AB V DD BA F A B ABF 00 01 10 11 CMOS Gates A X Y A AXY 00 01 10 11

13. EE42/100 Fall 2005 Prof. Fearing 13 Logic Functions, Symbols, & Notation “NOT” F = A TRUTH NAME SYMBOL NOTATIONTABLE FA ABF 000 010 100 111 “OR” F = A+B F A B AF 01 10 ABF 000 011 101 111 “AND” F = AB F A B

14. EE42/100 Fall 2005 Prof. Fearing 14 Logic Functions, Symbols, & Notation 2 “NOR” F = A+B ABF 000 011 101 110 “NAND” F = A B F A B ABF 001 011 101 110 “XOR” (exclusive OR) F = A + B F A B F A B ABF 001 010 100 110

15. EE42/100 Fall 2005 Prof. Fearing 15 Example: the half adder and the full adder AB Carry Sum A n+1 B n+1 C n+1 S n+1 CnCn SnSn AnAn BnBn C n-1 ABCarrySum 00 01 10 11

16. EE42/100 Fall 2005 Prof. Fearing 16 S 1 using sum-of-products: 1)Find where S 1 is 1 2)Write down each product of inputs which create a 1 3)Sum all of the products 4)Draw the logic circuit Logic Synthesis Example: Adder ABC n-1 CnCn SnSn 000 001 010 011 100 101 110 111 InputOutput A B C A B C + A B C

17. EE42/100 Fall 2005 Prof. Fearing 17 Karnaugh Maps Graphical approach to minimizing the number of terms in a logic expression: 1.Map the truth table into a Karnaugh map (see below) 2.For each 1, circle the biggest block that includes that 1 3.Write the product that corresponds to that block. 4.Sum all of the products A B 2-variable Karnaugh Map 01 1 0 A 1 0 BC 00011110 3-variable Karnaugh Map 4-variable Karnaugh Map CD 00011110 AB 00 01 11 10

18. EE42/100 Fall 2005 Prof. Fearing 18 ABC n-1 CnCn SnSn 00000 00101 01001 01110 10001 10110 11010 11111 InputOutput 00011110 00010 10111 A BC ACAB S 1 = AB + BC + AC Simplification of expression for S 1 : Karnaugh Map Example