1. The Serial Communication Interface (SCI) MC9S12-DP256 Chapter 11

2. SCI Asynchronous Serial I/O The 68HC12 SCI Interface Programming the SCI in WHYP SCI Interface Using Interrupts

4. SCI Asynchronous Serial I/O The 68HC12 SCI Interface Programming the SCI in WHYP SCI Interface Using Interrupts

13. WHYP Kernel ; 68HC12 KERNEL FOR WHYP12 ; Modified July, 2002 for the MC9S12DP256 ; Modified January, 2003 to add EEPROM words ; Copyright 1998 by Richard E. Haskell ; CSE Dept., Oakland University ; Rochester, Michigan 48309 ********************************************************* ******** Change the following five addresses ********* ******** for a particular 68HC12 environment ********* ********************************************************* REGBASE EQU $0000 ;register base RAMBASE EQU $1100 ;ram base EESTART EQU $0400 ;start address of EEPROM EESTOP EQU $0FFF ;stop address of EEPROM WHYPBASE EQU $4000 ;start of WHYP kernel ******** To make a turnkey system change START ******* ******** to the address of your main word. ******* ******** The default, MN1, will run WHYP. ******* *********************************************************** START EQU MN1

14. **** NOTE: SCI0 on MC9S12DP256 uses $C9-$CF instead of $C1-$C7 **** *********************************************************** SC0BDL EQU REGBASE+$C9 ;baud rate control SC0CR1 EQU REGBASE+$CA ;SCI control reg 1 SC0CR2 EQU REGBASE+$CB ;SCI control reg 2 SC0SR EQU REGBASE+$CC ;SCI status reg SC0DR EQU REGBASE+$CF ;SCI data reg COPCTL EQU REGBASE+$3C ;COP control reg ****** MC9S12DP256 uses different method to program EEPROM ******* EEPROT EQU REGBASE+$114 ;EEPROM Block Protect reg ESTAT EQU REGBASE+$115 ;EEPROM status reg ECMD EQU REGBASE+$116 ;EEPROM programming command reg RDRF EQU $20 ;SCSR mask STACK EQU RAMBASE+$100 ;system (return) stack DATSTK EQU RAMBASE+$80 ;data stack ****** WHYP System Variables ****** SP0 EQU RAMBASE ;initial data stack pointer RP0 EQU RAMBASE+$02 ;initial return stack pointer LAST EQU RAMBASE+$04 ;address called by CREATE

15. WHYP Kernel

16. SCI Asynchronous Serial I/O The 68HC12 SCI Interface Programming the SCI in WHYP SCI Interface Using Interrupts

17. \Serial Communications Interface - SCI HEX 00C8 CONSTANT SC0BDH \ SCI Baud Rate Control 00CA CONSTANT SC0CR1 \ SCI Control Register 1 00CB CONSTANT SC0CR2 \ SCI Control Register 2 00CC CONSTANT SC0SR1 \ SCI Status Register 1 00CF CONSTANT SC0DRL \ SCI Data (Read RDR, Write TDR) Registers needed to program SCI0

21. Communicating with a PC

22. \ Serial Communications Interface - SCI File: SCIECHO.WHP HEX 00C8 CONSTANT SC0BDH \ SCI0 Baud Rate Control 00CA CONSTANT SC0CR1 \ SCI0 Control Register 1 00CB CONSTANT SC0CR2 \ SCI0 Control Register 2 00CC CONSTANT SC0SR1 \ SCI0 Status Register 1 00CF CONSTANT SC0DRL \ SCI0 Data (Read RDR, Write TDR) : SCI0.INIT ( -- ) 0 SC0CR1 C! \ 8 DATA BITS 0C SC0CR2 C! \ ENABLE TE & RE 34 SC0BDH ! ; \ 9600 BAUD : TX! ( c -- ) \ send character BEGIN 7 SC0SR1 ?HI UNTIL SC0DRL C! ; : ?RX ( -- c tf | ff ) \ receive character 5 SC0SR1 ?HI IF SC0DRL C@ TRUE ELSE FALSE THEN ; : sci.echo ( -- ) SCI0.INIT BEGIN ?RX UNTIL TX! AGAIN ;

23. Testing SCI1 with the LOOP Function \ Serial Communications Interface - SCIFile: SCILOOP.WHP \ Works on a 9S12DP256 using the SCI1 port HEX 00D0 CONSTANT SC1BDH \ SCI1 Baud Rate Control 00D2 CONSTANT SC1CR1 \ SCI1 Control Register 1 00D3 CONSTANT SC1CR2 \ SCI1 Control Register 2 00D4 CONSTANT SC1SR1 \ SCI1 Status Register 1 00D7 CONSTANT SC1DRL \ SCI1 Data (Read RDR, Write TDR) : SCI1.INIT ( -- ) 80 SC1CR1 C! \ 8 DATA BITS - LOOP mode 0C SC1CR2 C! \ ENABLE TE & RE 34 SC1BDH ! ; \ 9600 BAUD : TX1! ( c -- ) \ send character BEGIN 7 SC1SR1 ?HI UNTIL SC1DRL C! ; : ?RX1 ( -- c tf | ff ) \ receive character 5 SC1SR1 ?HI IF SC1DRL C@ TRUE ELSE FALSE THEN ;

24. DECIMAL CREATE BAUD.RATE 110, 300, 600, 1200, 2400, 4800, 9600, 14400, 19200, 38400, CREATE BR.DIVISOR 4545, 1667, 833, 417, 208, 104, 52, 35, 26, 13, : FIND.N ( imax n -- ff | index tf ) 0 SWAP ROT \ 0 n imax 0 DO \ 0 n DUP I BAUD.RATE \ 0 n n ix pfa SWAP 2* + \ 0 n n pfa+2*ix @ = \ 0 n f IF \ 0 n DROP I TRUE \ 0 ix tf ROT LEAVE \ ix tf 0 THEN LOOP \ 0 n DROP ; \ 0 | ix tf

25. : BAUD ( n -- ) ( Ex. 1200 BAUD ) cr dup u. 10 SWAP FIND.N IF cr dup. 2* BR.DIVISOR + @ \ BR cr dup. SC1BDH ! THEN ; : sci1.test ( -- ) ASCII A \ c 26 FOR DUP TX1! \ c BEGIN \ wait for char ?RX1 UNTIL \ c c EMIT \ c 1+ \ c' NEXT DROP ;

26. \ Serial Communications Interface - SCI 9S12DP256 \ File: SCIREG.WHP LOAD HEX2ASC.WHP HEX 00C8 CONSTANT SC0BDH \ SCI0 Baud Rate Control 00CA CONSTANT SC0CR1 \ SCI0 Control Register 1 00CB CONSTANT SC0CR2 \ SCI0 Control Register 2 00CC CONSTANT SC0SR1 \ SCI0 Status Register 1 00CF CONSTANT SC0DRL \ SCI0 Data (Read RDR, Write TDR) 0250 CONSTANT PTM\ Port M 0258 CONSTANT PTP\ Port P 0260 CONSTANT PTH\ Port H 0268 CONSTANT PTJ\ Port J 0240 CONSTANT PTT\ Port T : SCI0.INIT ( -- ) 0 SC0CR1 C! \ 8 DATA BITS 0C SC0CR2 C! \ ENABLE TE & RE 34 SC0BDH ! ; \ 9600 BAUD : TX! ( c -- ) \ send character BEGIN 7 SC0SR1 ?HI UNTIL SC0DRL C! ; : ?RX ( -- c tf | ff ) \ receive character 5 SC0SR1 ?HI IF SC0DRL C@ TRUE ELSE FALSE THEN ;

27. : send.reg ( n -- ) DUP 4 RSHIFT \ high nibble hex2asc TX! 0F AND \ low nibble hex2asc TX! ; : send.regs ( -- ) SCI0.INIT BEGIN ?RX IF ASCII R = IF 0D TX! \ send CR PTM C@ send.reg \ send Port M 0D TX! \ send CR PTP C@ send.reg \ send Port P 0D TX! \ send CR PTH C@ send.reg \ send Port H 0D TX! \ send CR PTJ C@ send.reg \ send Port J 0D TX! \ send CR PTT C@ send.reg \ send Port T 0D TX! \ send CR THEN AGAIN ; DECIMAL

28. \ SCI Interface using interruptsFile: SCIINT.WHP \9S12DP256 LOAD HEX2ASC.WHP LOAD QUEUE.WHP HEX 00C8 CONSTANT SC0BDH \ SCI0 Baud Rate Control 00CA CONSTANT SC0CR1 \ SCI0 Control Register 1 00CB CONSTANT SC0CR2 \ SCI0 Control Register 2 00CC CONSTANT SC0SR1 \ SCI0 Status Register 1 00CF CONSTANT SC0DRL \ SCI0 Data (Read RDR, Write TDR) 0250 CONSTANT PTM\ Port M 0258 CONSTANT PTP\ Port P 0260 CONSTANT PTH\ Port H 0268 CONSTANT PTJ\ Port J 0240 CONSTANT PTT\ Port T 3FD6 CONSTANT SCI0.IVEC \ SCI0 user vector address : SCINT.INIT ( -- ) 0 SC0CR1 C! \ 8 DATA BITS 2C SC0CR2 C! \ ENABLE TE & RE, RX INT 34 SC0BDH C! ; \ 9600 BAUD INT: SCI.INTSER ( -- ) 5 SC0SR1 ?HI \ read to clear RDRF flag IF SC0DRL C@ QSTORE THEN RTI;

29. : SET.SCI.INTVEC( -- ) [ ' SCI.INTSER ] LITERAL SCI0.IVEC ! ; : send.reg ( n -- ) DUP 4 RSHIFT \ high nibble hex2asc TX! 0F AND \ low nibble hex2asc TX! ; \ Transmit all registers when 'R' is received : main.SCIports ( -- ) SEI INITQ SCINT.INIT SET.SCI.INTVEC CLI BEGIN CHECKQ IF 52 = \ if R IF 0D TX! \ send CR PTM C@ send.reg \ send Port M 0D TX! \ send CR PTP C@ send.reg \ send Port P 0D TX! \ send CR PTH C@ send.reg \ send Port H 0D TX! \ send CR PTJ C@ send.reg \ send Port J 0D TX! \ send CR PTT C@ send.reg \ send Port T 0D TX! \ send CR THEN AGAIN ;

30. Master-Slave SCI Communications \ MASTER - SEND 9-BIT REQUEST TO SLAVE 1 FOR ADCONV READ HEX 00C8 CONSTANT SC0BDH \ SCI0 Baud Rate Control 00CA CONSTANT SC0CR1 \ SCI0 Control Register 1 00CB CONSTANT SC0CR2 \ SCI0 Control Register 2 00CC CONSTANT SC0SR1 \ SCI0 Status Register 1 00CE CONSTANT SC0DRH \ SCI0 Data HI (R8, T8) 00CF CONSTANT SC0DRL \ SCI0 Data (Read RDR, Write TDR) : SCINIT.MASTER ( -- ) 10 SC0CR1 C! \ 9 data bits 40 SC0DRH C! \ set T8 0C SC0CR2 C! \ ENABLE TE & RE 34 SC0BDH C! ; \ 9600 BAUD : MAIN.MASTER ( -- ) SCINIT.MASTER BEGIN 1 TX! \ send 1 with T8 set BEGIN 5 SC0SR1 ?HI UNTIL SC0DRL C@. CR AGAIN ;

31. \ SCI SLAVE - INT ROUTINE WAKE UP - READ ADCONV - SEND LOAD ATD.WHP\ for ADCONV LOAD SCIREG.WHP\ SCI registers : SCINIT.SLAVE ( -- ) 18 SC0CR1 C! \ 9 DATA BITS - ADDR MARK WAKE 2E SCCR2 C! \ ENABLE TE & RE, REI 34 SC0BDH C! ; \ 9600 BAUD INT: SCISL.INTSER ( -- ) 5 SC0SR1 ?HI IF SC0DRL C@ 1 = \ if addr = 1 IF 2 ADCONV \ read A/D TX!\ and send it ELSE \ else 1 SC0CR2 HI \ go back to sleep THEN RTI; : SET.SCISL.INTVEC ( -- ) [ ' SCISL.INTSER ] LITERAL SCI.IVEC ! ; : MAIN.SLAVE ( -- ) SEI SCINIT.SLAVE SET.SCISL.INTVEC CLI ;

32. Summary

33. Exercises