1. Status – Week 275 Victor Moya

2. Simulator model Boxes. Boxes. Perform the actual work. Perform the actual work. Parameters: wires in, wires out, child boxes?. Parameters: wires in, wires out, child boxes?. A box can only access its own data, external data must come through wires (time!). A box can only access its own data, external data must come through wires (time!). A box: A box: whatever you do in 1+ cycle or whatever whatever you do in 1+ cycle or whatever or or what a piece of hardware does what a piece of hardware does Wires. Wires. Communication between boxes. Communication between boxes. Carry the simulator time: 1+ cycle. Carry the simulator time: 1+ cycle. Parameters: bandwidth, latency. Parameters: bandwidth, latency.

3. Problems Must be 0 latency for wires forbidden? Must be 0 latency for wires forbidden? How do you divide the hardware in boxes? How do you divide the hardware in boxes? What happens if a two boxes must communicate in the same cycle? What happens if a two boxes must communicate in the same cycle?

4. Vertex Shader Core Just a SIMD 4 stage processor. Just a SIMD 4 stage processor. No multithreading. No multithreading.

5. Vertex Shader Core

6. Vertex Shader Core Model Instruction Fetch Instruction Fetch Sends the instruction byte code pointed by the current PC to Decode/Register box (latency 1). Sends the instruction byte code pointed by the current PC to Decode/Register box (latency 1). Decode/Register Decode/Register Calculates next PC (sequential, jump, conditional jump, calls, return, indirect) and sends it to Instruction Fetch (latency 1). Calculates next PC (sequential, jump, conditional jump, calls, return, indirect) and sends it to Instruction Fetch (latency 1). Reads up to three source operands from the register files (Vertex Input, Constant, Temporary, Address) and sends them to Execute with the instruction operation code (latency1). Reads up to three source operands from the register files (Vertex Input, Constant, Temporary, Address) and sends them to Execute with the instruction operation code (latency1). Gets incoming result (flags + operation result) from execute and write them in the register files (flags, Vertex Output, Temporary). Gets incoming result (flags + operation result) from execute and write them in the register files (flags, Vertex Output, Temporary). Execute Execute Performes an operation with the operands received with from the Decode/Register box and sends the result back to Decode/Register box with 1+ latency. Performes an operation with the operands received with from the Decode/Register box and sends the result back to Decode/Register box with 1+ latency.

7. Vertex Shader Core Model