1. 1 5-bit Decimation Filter Loretta Chui, Xiao Zhuang Hock Cheah, Gita Kazemi Advisor: David Parent December 6, 2004

2. 2 Agenda Abstract Introduction Project Details Results Cost Analysis Conclusions

3. 3 Abstract We designed a 5-bit Decimation Filter, which can be used to sample the output of an A/D converter at a lower rate. Our system operates at 143 MHz, uses less than 100 mW of power, and occupies an area of 360 x 280  m 2.

4. 4 Introduction The averaging filter used at the output of an A/D converter is called a decimation filter. The decimation filter samples the incoming data until the sum of k inputs has been accumulated. Then, the sum is dumped into an output flip-flop. Through this process, the filter reduces (decimates) the output frequency by k times.

5. 5

6. 6 Longest Path Calculations for the 7-bit Adder

7. 7 Longest Path Calculations for the D-Flipflops

8. 8 Decimation Filter Schematic

9. 9 System Counter

10. 10 Decimation Filter Layout

11. 11 LVS Verification

12. 12 Simulations (schematic)

13. 13 Simulations (extracted)

14. 14 Impulse Input Impulse Output Step Input Step Output

15. 15 DFF Rise Time For Hold DFF Fall Time For Hold

16. 16 DFF Rise Time for Setup DFF Fall Time for Setup

17. 17 Power Waveform

18. 18 Cost Analysis Estimated time spent on each phase of the project: –verifying logic (1 week) –verifying timing (1 week) –layout (3 weeks) –post extracted timing (1.5 weeks)

19. 19 Conclusion We designed a decimation filter, which samples and sums the incoming data 3 inputs at a time. Through this process, the filter reduces (decimates) the output frequency by a factor of 3. Our design met all specifications except for timing because our adder was too slow. We propose the use of an alternative design, which uses a mux select to implement a faster adder.

20. 20 Alternative Adder using a Mux Select

21. 21 Lessons Learned It would be helpful to students to use a layered approach for the chip layout by creating instances of individual parts instead of copy and paste to improve debugging capabilities. It would be helpful if professors could spend some time to cover testing methodology.

22. 22 Acknowledgements Thanks to our family and friends who missed us for the past 3 months. Thanks to Cadence Design Systems for the VLSI lab. Thanks to Dr. Parent and John for their advice and great patience.