1. Encryption Transaction with 3DES Team W2 Yervant Dermenjian (W21) Taewan Kim (W22) Evan Mengstab(W23) Xiaochun Zhu(W24) Objective: To implement a secure credit card transaction using 3DES encryption using Kerberos-style authentication. Current Stage: Final Changes 04/05/2004 Design Manager: Rebecca Miller

2. Current Status  Design Proposal (100% done)  Architecture Proposal (100% done)  Size Estimate and Floor Plan (100% done)  Full-chip Transistor-level Schematic (100% done)  Component Layout & Simulation (100% done)  Top-Level Layout (100% done)  Spice simulation of the entire chip (Successful) Improve Performance Improve Performance

3. Simulation Strategy  Simulate Entire Chip  Use same inputs from C and Verilog verification Encryption ensures multiple vectors over critical path Encryption ensures multiple vectors over critical path Each iteration tests different pattern over critical path Each iteration tests different pattern over critical path  Each time an iteration is run, SBOX determines new values that will initiate critical path  Run simulation for 20 clock cycles Will not produce final output but… Will not produce final output but… Values at each node should match Verilog Values at each node should match Verilog

4. Critical Path 00000000D8D8DBBC D8D8DBBCE73AED4F 80FF828E80FFC887 80FB848480FFC68C 80FFC68C0905717 Mux -> Expand -> XOR -> SBOX -> P Permutation -> XOR -> Mux

5. Spice Simulation 150 MHz simulation

6. Spice Simulation 150 MHz simulation

7. Problems Simulating Degredation of Vdd! away from pin Modules near vdd! pin work correctly Modules near vdd! pin work correctly Modules further away have a lower vdd! Do not pass full 1.8 volts when PMOS passes vdd signal Modules further away have a lower vdd! Do not pass full 1.8 volts when PMOS passes vdd signal Possible Solutions Investigated Add more global Vdd! connections Add more global Vdd! connections Buffer weak ROM input signals Buffer weak ROM input signals Improve rise/fall times of 48-bit xor ROM input Improve rise/fall times of 48-bit xor ROM input Add M1_P to Ground contacts throughout ROMs Add M1_P to Ground contacts throughout ROMs

8. Vdd! Problems  Simulation of Program Control and ROM using vdd! and gnd! wiring from top-level  Outputs all very low Actual lengths from top level design 400mV Additional M1_P contacts added to ROM

9. Conclusions / Solutions  Conclusions Vdd and Ground are not assumed to be infinite strength Vdd and Ground are not assumed to be infinite strength Something is killing our vdd! strength Something is killing our vdd! strength  Solutions Nwell contacts on Vdd! Lines improved PCROM sims Nwell contacts on Vdd! Lines improved PCROM sims  Status Improvements / Changes were made Improvements / Changes were made Simulation successful at 150MHz Simulation successful at 150MHz

10. Questions ?